199758 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details Error catch memory
TECHNIQUES FOR DETECTING A STATE OF A BUS
#2TESTING METHOD AND TESTING SYSTEM
#3HEALTH SCAN FOR CONTENT ADDRESSABLE MEMORY
#4TECHNIQUES FOR DETECTING A STATE OF A BUS
#5TESTING PARITY AND ECC LOGIC USING MBIST
#6Memory Verification Using Processing-in-Memory
#7CONTROL CIRCUIT, MEMORY SYSTEM AND CONTROL METHOD
#8Detect whether die or channel is defective to confirm temperature data
#9Health scan for content addressable memory
#10Control circuit, memory system and control method
#11Techniques for detecting a state of a bus
#12Detect whether die or channel is defective to confirm temperature data
#13Fail bit repair solution determination method and device
#14Memory devices and methods for managing error regions
#15Calibration for integrated memory assembly
#16Block quality classification at testing for non-volatile memory, and multiple bad block flags for product diversity
#17Apparatuses and methods for direct access hybrid testing
#18Layered semiconductor device, and production method therefor
#19MEMORY DEVICE CONTROLLER
#20Memory devices and methods for managing error regions
#21Shared error detection and correction memory
#22System architecture method and apparatus for adaptive hardware fault detection with hardware metrics subsystem
#23Memory circuit and testing method thereof
#24FUSE-BLOWING SYSTEM AND METHOD FOR OPERATING THE SAME
#25Integrated circuit fault detection
#26Memory devices and methods for managing error regions
#27Non-volatile memory repair circuit
#28Data processing
#29Memory test system and an operating method thereof
#30FAILURE PREVENTION OF BUS MONITOR
#31Test mode control circuit
#32Data processing apparatus for handling page fault using predefind bit patterns and a method thereof
#33Embedded memory testing with storage borrowing
#34Apparatuses and methods for selective determination of data error repair
#35Memory with bit line short circuit detection and masking of groups of bad bit lines
#36MEMORY DEVICE
#37Shared error detection and correction memory
#38Memory and logic lifetime simulation systems and methods
#39Technologies for estimating remaining life of integrated circuits using on-chip memory
#40On-chip diagnostic circuitry monitoring multiple cycles of signal samples
#41Test mode control circuit
#42Background memory test apparatus and methods
#43Memory device for performing error correction code operation and redundancy repair operation
#44Integrated circuit defect detection and repair
#45Method and apparatus for optimized memory test status detection and debug
#46Memory block quality identification in a memory
#47Semiconductor device and operation method thereof
#48Integrated circuit and method for testing semiconductor devices using the same
#49Semiconductor integrated circuit capable of performing self-test
#50MEMORY TESTING AND FAILURE DATA FILTERING
#51Memory devices and methods for managing error regions
#52Semiconductor storing device and redundancy method thereof
#53System on chip including built-in self test circuit and built-in self test method thereof
#54Apparatus for capturing results of memory testing
#55Systems and methods for testing pages of data stored in a memory module
#56MRAM self-repair with BIST logic
#57Storage medium and transmittal system utilizing the same
#58Apparatus, system, and method for wear management
#59Memory devices and methods for managing error regions
#60SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT
#61Fully-buffered dual in-line memory module with fault correction
#62Memory devices and method for error test, recordation and repair
#63Method of operating memory controller, memory controller, memory device and memory system
#64SEMICONDUCTOR INTEGRATED CIRCUIT, FAILURE DIAGNOSIS SYSTEM AND FAILURE DIAGNOSIS METHOD
#65Nonvolatile memory device and method for operating the same
#66TESTING METHOD, NON-TRANSITORY, COMPUTER READABLE STORAGE MEDIUM AND TESTING APPARATUS
#67Memory devices and methods for managing error regions
#68Device and method for repair analysis
#69Semiconductor device and manufacturing method thereof
#70Method for error test, recordation and repair
#71FAULT DIAGNOSIS IN A MEMORY BIST ENVIRONMENT
#72Centralized MBIST failure information
#73MEMORY ERRORS AND REDUNDANCY
#74Fully-buffered dual in-line memory module with fault correction
#75Fully-buffered dual in-line memory module with fault correction
#76Error detection, documentation, and correction in a flash memory device
#77Accessing memory cells in a memory circuit
#78Memory controlling apparatus and method
#79Memory apparatus and testing method thereof
#80System and method for increasing the extent of built-in self-testing of memory and circuitry
#81Fault diagnosis for non-volatile memories
#82Method and system for performing a double pass NTH fail bitmap of a device memory
#83Method, system and computer-readable code to test flash memory
#84Semiconductor memory device
#85Memory devices and methods for managing error regions
#86Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array
#87Resistance change memory
#88Processor and method for controlling storage-device test unit
#89Semiconductor integrated circuit and method for controlling semiconductor integrated circuit
#90Apparatus, system, and method for retiring storage regions
#91Flash memory device and method of testing the flash memory device
#92Computer apparatus
#93Computer apparatus and processor diagnostic method
#94Semiconductor memory device and method for testing the same
#95Semiconductor memory device and system including the same
#96Memory system with ECC-unit and further processing arrangement
#97Semiconductor testing device and method of testing semiconductor memory
#98Integrated circuit that stores first and second defective memory cell addresses
#99Programmable pulsewidth and delay generating circuit for integrated circuits
#100MEMORY DEVICE
#101System and method for increasing the extent of built-in self-testing of memory and circuitry
#102Memory diagnosis method
#103Semiconductor device
#104Methods for performing fail test, block management, erasing and programming in a nonvolatile memory device
#105Built-in self-repair method for NAND flash memory and system thereof
#106Redundant bit patterns for column defects coding
#107FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS
#108Memory circuit
#109Method of manufacturing flash memory device
#110Maintaining Error Statistics Concurrently Across Multiple Memory Ranks
#111Self-diagnostic scheme for detecting errors
#112Method of Testing an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Integrated Circuit
#113Method for creating a memory defect map and optimizing performance using the memory defect map
#114SEMICONDUCTOR STORAGE DEVICE
#115Memory with dynamic redundancy configuration
#116System-in-package and method of testing thereof
#117Programmable pulsewidth and delay generating circuit for integrated circuits
#118Integrated circuit and test method
#119Memory structure, repair system and method for testing the same
#120Parallel instruction processing and operand integrity verification
#121Efficient memory product for test and soft repair of SRAM with redundancy
#122Test apparatus for testing a memory and electronic device housing a circuit
#123Partial good integrated circuit and method of testing same
#124Shared latch for memory test/repair and functional operations
#125Uncorrectable error detection utilizing complementary test patterns
#126DESIGN STRUCTURE USED FOR REPAIRING EMBEDDED MEMORY IN AN INTEGRATED CIRCUIT
#127BIST CIRCUIT DEVICE AND SELF TEST METHOD THEREOF
#128Redundancy programming for a memory device
#129Semiconductor memory device and redundancy method of the same
#130Using a single bank of efuses to successively store testing data from multiple stages of testing
#131Smart card and method of testing smart card
#132Partial good integrated circuit and method of testing same
#133Memory device including self-ID information
#134Programmable address space built-in self test (BIST) device and method for fault detection
#135METHOD AND SYSTEM FOR TESTING A MEMORY DEVICE
#136Method and apparatus for testing data steering logic for data storage having independently addressable subunits
#137Semiconductor memory device storing repair information avoiding memory cell of fail bit operating method thereof
#138Generation and use of system level defect tables for main memory
#139Memory block quality identification in a memory device
#140Fully-buffered dual in-line memory module with fault correction
#141Fully-buffered dual in-line memory module with fault correction
#142Fully-buffered dual in-line memory module with fault correction
#143Fully-buffered dual in-line memory module with fault correction
#144Method for error test, recordation and repair
#145Semiconductor memory device
#146Nonvolatile semiconductor memory device and method of self-testing the same
#147Storage efficient memory system with integrated BIST function
#148Method of managing fails in a non-volatile memory device and relative memory device
#149RRAM controller built in self test memory
#150Semiconductor memory devices and a method thereof
#151Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing
#152Volatile semiconductor memory
#153Error detection, documentation, and correction in a flash memory device
#154Memory block quality identification in a memory device
#155Error detection, documentation, and correction in a flash memory device
#156RAM testing apparatus and method
#157Semiconductor memory device with test circuit
#158Method for self-correcting cache using line delete, data logging, and fuse repair correction
#159Efficient method of test and soft repair of SRAM with redundancy
#160System for storing device test information on a semiconductor device using on-device logic for determination of test results
#161Memory buffer
#162Electronic circuit
#163Memory block quality identification in a memory device
#164Semi-conductor component, as well as a process for the in-or output of test data
#165Semi-conductor component, as well as a process for the reading of test data
#166Integrated semiconductor memory
#167Built-in self diagnosis device for a random access memory and method of diagnosing a random access
#168Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
#169System and method of improving memory yield in frame buffer memory using failing memory location
#170Semiconductor memory device for build-in fault diagnosis
#171Central processing unit and micro computer
#172Apparatus and method for testing a memory device with multiple address generators
#173Memory device including self-ID information
#174On-chip and at-speed tester for testing and characterization of different types of memories
#175Memory device with built-in test function and method for controlling the same
#176Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
#177System-in-package and method of testing thereof
#178MRAM having error correction code circuitry and method therefor
#179Multiple on-chip test runs and repairs for memories
#180Magnetic memory which compares compressed fault maps
#181Integrated circuit for storing operating parameters
#182Semiconductor memory device
#183Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data
#184Semiconductor device and testing apparatus for semiconductor device
#185Semiconductor memory, method of testing semiconductor memory and method of manufacturing semiconductor memory
#186Method and apparatus for dynamically hiding a defect in an embedded memory
#187Self-test architecture to implement data column redundancy in a RAM
#188Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
#189Partial good integrated circuit and method of testing same
#190Memory testing apparatus and method
#191Repair apparatus and method for semiconductor memory device to be selectively programmed for wafer-level test or post package test
#192Apparatus and method for reading out defect information items from an integrated chip
#193Semiconductor circuit and method for testing, monitoring and application-near setting of a semiconductor circuit
#194Memory device and method of storing fail addresses of a memory cell
#195Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrate circuit device
#196Semiconductor memory apparatus and self-repair method
#197Apparatuses and methods for direct access hybrid testing
#198Method and apparatus for detecting a row or a column of a memory to repair without reporting all corresponding defective memory cells
#199Detecting and managing bad columns
#200Detecting and managing bad columns