199763 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details; Address generation devices; Devices for accessing memories, e.g. details of addressing circuits Manipulation of word size
VARIABLE PAGE SIZE ARCHITECTURE
#2Wordline capacitance balancing
#3Variable page size architecture
#4ECC in integrated memory assembly
#5Wordline capacitance balancing
#6Wordline capacitance balancing
#7Variable page size architecture
#8Content addressable memory with match hit quality indication
#9Content addressable memory with match hit quality indication
#10Variable page size architecture
#11Memory integrity
#12Semiconductor memory device
#13Error correction coding over multiple memory pages
#14Semiconductor memory and method for testing the same
#15Semiconductor memory and method for testing the same
#16Semiconductor memory device and method for testing the same
#17Memory test circuit
#18Memory testing system and method
#19Semiconductor memory and method for testing the same
#20Memory-module board layout for use with memory chips of different data widths
#21Memory having a portion that can be switched between use as data and use as error correction code (ECC)
#22Memory chip and semiconductor device using the memory chip and manufacturing method of those
#23Memory device capable of changing data output mode
#24Method and apparatus for separating native, functional and test configurations of memory
#25Memory device including parallel test circuit