199764 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details; Address generation devices; Devices for accessing memories, e.g. details of addressing circuits Address conversion or mapping, i.e. logical to physical address
ERROR DETECTION
#2FAILURE ANALYSIS DEVICE AND FAILURE ANALYSIS METHOD
#3APPARATUSES AND METHODS FOR TESTING MEMORY DEVICES
#4Bit retiring to mitigate bit errors
#5METHOD FOR OPERATING A MEMORY DEVICE AND MEMORY DEVICE THEREOF
#6ERROR REMAPPING
#7Memory device virtual blocks using half good blocks
#8Memory system and method for controlling nonvolatile memory during command processing without replacing defective blocks
#9Error remapping
#10Bit retiring to mitigate bit errors
#11Memory device virtual blocks using half good blocks
#12Modifiable repair solutions for a memory array
#13Adjustable column address scramble using fuses
#14Memory system and method for controlling nonvolatile memory
#15Error remapping
#16Memory system and method for controlling nonvolatile memory
#17Effective chip yield for artificial intelligence integrated circuit with embedded memory
#18Scan chain techniques and method of using scan chain structure
#19Semiconductor device, memory test method for semiconductor device, and test pattern generation program
#20Semiconductor device
#21Semiconductor memory device and operating method
#22Memory system and method for controlling nonvolatile memory
#23FAILURE PREVENTION OF BUS MONITOR
#24Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion
#25Memory device and operating method thereof
#26Background memory test apparatus and methods
#27Apparatus and method for selective sub word line activation for reducing testing time
#28MEMORY MAPPING
#29Combined rank and linear address incrementing utility for computer memory test operations
#30System and method to emulate an electrically erasable programmable read-only memory
#31Memory device selecting different column selection lines based on different offset values and memory system including the same
#32Generic address scrambler for memory circuit test engine
#33Methods and devices for determining logical to physical mapping on an integrated circuit
#34Systems and methods for storing and retrieving a defect map in a DRAM component
#35Semiconductor test device and method of generating address scramble using the same
#36SEMICONDUCTOR TEST METHOD, SEMICONDUCTOR TEST APPARATUS, AND COMPUTER READABLE MEDIUM
#37Semiconductor memory and system
#38MEMORY ACCESS METHOD
#39Semiconductor memory test device and method thereof
#40ADDRESS TRANSLATION BETWEEN A MEMORY CONTROLLER AND AN EXTERNAL MEMORY DEVICE
#41SEMICONDUCTOR MEMORY DEFECT ANALYSIS METHOD AND DEFECT ANALYSIS SYSTEM
#42Test apparatus, program, and test method
#43Controller for non-volatile memories and methods of operating the memory controller
#44Buffered memory having a control bus and dedicated data lines
#45Error checking and correction (ECC) system and method
#46Semiconductor integrated circuit and testing method thereof
#47Semiconductor memory test device and method thereof
#48Methods of memory bitmap verification for finished product
#49Method for SRAM bitmap verification
#50Semiconductor memory component and method for testing semiconductor memory components
#51Method and apparatus for memory self testing
#52Test data topology write to memory using latched sense amplifier data and row address scrambling
#53Semiconductor memory and method of testing semiconductor memory
#54Integrated semiconductor memory device including sense amplifiers
#55Semi-conductor component, as well as a process for the in-or output of test data
#56Method and apparatus for enabling a user to determine whether a defective location in a memory device has been remapped to a redundant memory portion
#57Algorithm pattern generator for testing a memory device and memory tester using the same
#58Built-in self diagnosis device for a random access memory and method of diagnosing a random access
#59Large scale integrated circuit and at speed test method thereof
#60Test apparatus with memory data converter for redundant bit and word lines
#61Apparatus and method for testing a memory device with multiple address generators
#62Method for testing and programming memory devices and system for same
#63Configurable width buffered module having switch elements
#64Embedded micro computer unit (MCU) for high-speed testing using a memory emulation module and a method of testing the same
#65Defective data site information storage
#66Configurable width buffered module having splitter elements
#67Configurable width buffered module having flyby elements
#68Memory device providing bad column repair and method of operating same
#69Accelerated translation power recovery
#70Memory controller with enhanced block management techniques