199850 ⎘
Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store; Sense amplifier related aspects Sense amplifier drivers
SEMICONDUCTOR DEVICES PROVIDING TEST MODE RELATED TO RELIABILITY
#2SEMICONDUCTOR STORAGE DEVICE COMPRISING A REPLICA BIT LINE CIRCUIT
#3SEMICONDUCTOR DEVICES PROVIDING TEST MODE RELATED TO RELIABILITY
#4SEMICONDUCTOR STORAGE DEVICE
#5Read accelerator circuit
#6SEMICONDUCTOR APPARATUS
#7Semiconductor memory apparatus
#8Semiconductor memory with sense amplifier
#9Semiconductor memory with sense amplifier
#10Power management for a memory device
#11Low voltage sensing scheme having reduced active power down standby current
#12Semiconductor memory with sense amplifier
#13Low voltage sensing scheme having reduced active power down standby current
#14LOW POWER MEMORY CONTROL CIRCUITS AND METHODS
#15System and method of operating a memory device
#16Low voltage sensing scheme having reduced active power down standby current
#17Semiconductor memory device having a plurality of sense amplifier circuits
#18SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL SENSE AMPLIFIER WITH ON/OFF CONTROL
#19Method and apparatus for synchronization of row and column access operations
#20SEMICONDUCTOR DEVICE
#21Digitally-controllable delay for sense amplifier
#22Method and apparatus for synchronization of row and column access operations
#23Semiconductor memory with sense amplifier and driver transistor rows
#24Semiconductor memory apparatus
#25Memory circuit and method of sensing a memory element
#26METHOD AND APPARATUS FOR SYNCHRONIZATION OF ROW AND COLUMN ACCESS OPERATIONS
#27Low power memory architecture
#28Semiconductor memory device enhancing reliability in data reading
#29Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages
#30SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF
#31Method and apparatus for synchronization of row and column access operations
#32Sense amplifier biasing method and apparatus
#33Semiconductor memory device with normal and over-drive operations
#34Low voltage sensing scheme having reduced active power down standby current
#35Semiconductor memory device capable of controlling drivability of overdriver
#36Method for controlling a semiconductor apparatus
#37SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME
#38Semiconductor memory device including a sense amplifier having a reduced operating current
#39Memory device with configurable delay tracking
#40Semiconductor memory apparatus for allocating different read/write operating time to every bank
#41Semiconductor memory device
#42Apparatus and Method for Supplying Power in Semiconductor Device
#43Semiconductor memory device and control method thereof
#44Semiconductor memory device
#45Over driving pulse generator
#46Semiconductor memory device
#47Method and apparatus for synchronization of row and column access operations
#48Circuit for generating pulses for semiconductor memory apparatus
#49Semiconductor memory device
#50Semiconductor memory
#51Memory transistor gate oxide stress release and improved reliability
#52Semiconductor storage device
#53Semiconductor device
#54Memory transistor gate oxide stress release and improved reliability
#55Low power memory architecture
#56Semiconductor memory apparatus
#57Sense amplifier circuit in semiconductor memory device and driving method thereof
#58Control system for a dynamic random access memory and method of operation thereof
#59Sense amplifier control circuit and semiconductor device using the same
#60Noise suppression in memory device sensing
#61Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with drivability for each
#62Sense amplifier flip flop
#63Method of operating a semiconductor device and the semiconductor device
#64Integrated circuit and method of operating such a circuit
#65Automatic address transition detection (ATD) control for reduction of sense amplifier power consumption
#66Temperature sensing circuit, voltage generation circuit, and semiconductor storage device
#67SEMICONDUCTOR INTEGRATED CIRCUIT
#68Memory device and method of operating the same
#69Non-volatile memory and method with reduced source line bias errors
#70Non-volatile memory and method with improved sensing
#71Semiconductor memory device and method for driving semiconductor memory device
#72Differential amplifier circuit
#73Bit-line sense amplifier driver
#74Semiconductor memory
#75Low power memory control circuits and methods
#76Semiconductor memory device and driving method thereof
#77Semiconductor memory device
#78Sense amplifier over driver control circuit and method for controlling sense amplifier of semiconductor device
#79Over-driving circuit for semiconductor memory device
#80Semiconductor memory device and method for driving bit line sense amplifier thereof
#81Over-driving circuit in semiconductor memory device
#82Core voltage generator and method for generating core voltage in semiconductor memory device
#83Driving signal generator for bit line sense amplifier driver
#84Semiconductor memory device
#85Semiconductor memory device
#86Low voltage sensing scheme having reduced active power down standby current
#87Layout for distributed sense amplifier driver in memory device
#88Internal voltage supply circuit
#89Memory device for retaining data during power-down mode and method of operating the same
#90Semiconductor device and testing method thereof
#91Semiconductor memory device
#92Semiconductor memory device
#93Overdrive period control device and overdrive period determining method
#94Noise suppression in memory device sensing
#95Local bit select circuit with slow read recovery scheme
#96Memory devices and methods of operation thereof using interdependent sense amplifier control
#97Dual stage DRAM memory equalization
#98Integrated DRAM memory device
#99Sense amplifier driver and semiconductor device comprising the same
#100Circuit arrangement having security and power saving modes
#101Dynamical adaptation of memory sense electronics
#102Method and apparatus for synchronization of row and column access operations
#103Internal voltage supply circuit
#104Low voltage sense amplifier for operation under a reduced bit line bias voltage
#105Memory circuit with supply voltage flexibility and supply voltage adapted performance
#106Semiconductor memory apparatus and activation signal generation method for sense amplifier
#107Noise suppression in memory device sensing
#108Dual stage DRAM memory equalization
#109Semiconductor storage apparatus
#110Semiconductor device
#111Semiconductor memory device having local sense amplifier with on/off control
#112Method of operating a semiconductor device and the semiconductor device
#113Semiconductor memory device and control method for semiconductor memory device
#114Semiconductor memory with sense amplifier equalizer having transistors with gate oxide films of different thicknesses
#115Programmable sense amplifier timing generator
#116Semiconductor memory device having enhanced sense amplifier
#117Semiconductor memory device capable of controlling drivability of overdriver
#118Apparatus and method for supplying power in semiconductor device
#119Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with different drivability for each
#120Semiconductor memory device
#121Semiconductor memory device
#122Semiconductor memory device enhancing reliability in data reading
#123Method and circuit for dynamic read margin control of a memory array
#124Semiconductor integrated circuit device
#125Semiconductor memory device for reducing write recovery time
#126Semiconductor integrated circuit
#127Sense amplifier thermal correction scheme
#128Low voltage sense amplifier for operation under a reduced bit line bias voltage
#129Method of apparatus for enhanced sensing of low voltage memory
#130Dual power sensing scheme for a memory device
#131Semiconductor device having sense amplifier driver with capacitor affected by off current
#132Low-voltage sense amplifier and method
#133Resetable control circuit devices for sense amplifiers
#134Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM)
#135Semiconductor memory device
#136Semiconductor memory device using VSS or VDD bit line precharge approach without reference cell
#137Method and apparatus for synchronization of row and column access operations
#138Process for controlling the read amplifiers of a memory and corresponding memory integrated circuit
#139Semiconductor memory device having over-driving scheme
#140Semiconductor device