199856 ⎘
Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store; Aspects relating to interfaces of memory device to external buses Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
Vehicle memory system based on 3D memory and method operating thereof
#2Adjustable column address scramble using fuses
#3Apparatuses and methods for data movement
#4Semiconductor device and system using the same
#5Semiconductor device and system using the same
#6Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#7Semiconductor device and system using the same
#8Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#9Apparatuses and methods for operations using compressed and decompressed data
#10Apparatuses and methods for data movement
#11Securely sharing a memory between an embedded controller (EC) and a platform controller hub (PCH)
#12Refresh in memory based on monitor array threshold drift
#13Refresh in memory based on a set margin
#14Contention-free dynamic logic
#15VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS
#16Method of propagating magnetic domain wall in magnetic devices
#17Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#18Apparatuses and methods for data movement
#19Memory macro and semiconductor integrated circuit device
#20Semiconductor device and system using the same
#21Apparatuses and methods for operations using compressed and decompressed data
#22Dynamic Random Access Memory For Communications Systems
#23Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#24Memory device with internal combination logic
#25Refresh request queuing circuitry
#26Dynamic random access memory with configurable refresh rate for communications systems
#27Semiconductor memory device capable of preventing negative bias temperature instability (NBTI) using self refresh information
#28Protection against word line failure in memory devices
#29System on chip including built-in self test circuit and built-in self test method thereof
#30System and method for data read of a synchronous serial interface NAND
#31Systems and methods for testing pages of data stored in a memory module
#32Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#33Dynamic random access memory for communications systems
#34Memory device with internal combination logic
#35Configurable embedded memory system
#36Memory apparatus
#37Refresh request queuing circuitry
#38Method of error correction of a memory
#39EDRAM refresh in a high performance cache architecture
#40Fully-buffered dual in-line memory module with fault correction
#41Digit line comparison circuits
#42Method and apparatus for synchronizing data from memory arrays
#43SEMICONDUCTOR DEVICE HAVING A THIN FILM CAPACITOR AND METHOD FOR FABRICATING THE SAME
#44Concurrent memory bank access and refresh request queuing
#45Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#46Lengthening life of a limited life memory
#47Integrated circuit having memory array including ECC and column redundancy and method of operating same
#48Memory apparatus and method using erasure error correction to reduce power consumption
#49System and method for data read of a synchronous serial interface NAND
#50Passgate for dynamic circuitry
#51ERROR CORRECTION CIRCUIT AND METHOD, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE CIRCUIT
#52Optimized solid electrolyte for programmable metallization cell devices and structures
#53eDRAM refresh in a high performance cache architecture
#54Sense-amplification with offset cancellation for static random access memories
#55EMBEDDED STORAGE APPARATUS AND TEST METHOD THEREOF
#56Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
#57No-disturb bit line write for improving speed of eDRAM
#58Microelectronic programmable device and methods of forming and programming the same
#59High performance data rate system for flash devices
#60Flash memory
#61Digit line comparison circuits
#62DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD OF DETERMINING REFRESH CYCLE THEREOF
#63Memory refresh system and operating method thereof
#64Method of detecting error in a semiconductor memory device
#65Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#66Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#67System in package integrated circuit with self-generating reference voltage
#68Fully-buffered dual in-line memory module with fault correction
#69Fully-buffered dual in-line memory module with fault correction
#70Processor instruction cache with dual-read modes
#71SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities
#72Switched-capacitor charge pumps
#73Lengthening life of a limited life memory
#74Hybrid memory device with single interface
#75Semiconductor integrated circuit
#76Soft error protection in individual memory devices
#77Microelectronic programmable device and methods of forming and programming the same
#78Method and apparatus for synchronizing data from memory arrays
#79Concurrent memory bank access and refresh retirement
#80Method and system for controlling refresh to avoid memory cell data losses
#81Method and apparatus for a robust embedded interface
#82Optimized solid electrolyte for programmable metallization cell devices and structures
#83Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
#84Selectively controlled memory
#85Threshold evaluation of EPROM cells
#86Scaleable memory systems using third dimension memory
#87Logic embedded memory having registers commonly used by macros
#88Memory apparatus and method using erasure error correction to reduce power consumption
#89Dynamic random access memory device and method of determining refresh cycle thereof
#90Flash memory
#91No-disturb bit line write for improving speed of eDRAM
#92Switched-capacitor charge pumps
#93System and method for data read of a synchronous serial interface NAND
#94Semiconductor memory device
#95Semiconductor memory device
#96Electronic memory device
#97Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#98Semiconductor integrated circuit device
#99Electronic Circuit with Memory for Which a Threshold Level is Selected
#100Microelectric programmable device and methods of forming and programming the same
#101System and method for using a DLL for signal timing control in a eDRAM
#102Optimized solid electrolyte for programmable metallization cell devices and structures
#103DISPLAY DRIVER IC HAVING EMBEDDED DRAM
#104Method and apparatus for synchronizing data from memory arrays
#105Method and apparatus for variable memory cell refresh
#106Processor instruction cache with dual-read modes
#107Scalable embedded DRAM array
#108Scalable embedded DRAM array
#109Method and system for controlling refresh to avoid memory cell data losses
#110Integrated circuit having a memory with process-voltage-temperature control
#111Circuit and method for patching for program ROM
#112Scaleable memory systems using third dimension memory
#113Semiconductor memory apparatus capable of detecting error in data input and output
#114Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)
#115Semiconductor integrated circuit
#116Methods and apparatus to provide refresh for global out of range read requests
#117Error correction circuit and method, and semiconductor memory device including the circuit
#118Semiconductor integrated circuit device
#119Memory controller and semiconductor memory device
#120Random access memory including test circuit
#121Method and system for controlling refresh to avoid memory cell data losses
#122Optimized solid electrolyte for programmable metallization cell devices and structures
#123Random access memory including multiple state machines
#124Integrated circuit having memory array including ECC and column redundancy and method of operating the same
#125Flash memory device including multi-buffer block
#126Hybrid memory device with single interface
#127Dynamic RAM storage techniques
#128Contention-free hierarchical bit line in embedded memory and method thereof
#129Semiconductor storage device and refresh control method therefor
#130Semiconductor memory in which error correction is performed by on-chip error correction circuit
#131HIGH SPEED BIST UTILIZING CLOCK MULTIPLICATION
#132Flash memory
#133Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
#134Semiconductor memory device and memory system including the same
#135Bit line precharge in embedded memory
#136Embedded memory and methods thereof
#137Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#138Memory device with hierarchy bit line
#139Method and apparatus for synchronizing data from memory arrays
#140Fully-buffered dual in-line memory module with fault correction
#141Fully-buffered dual in-line memory module with fault correction
#142Fully-buffered dual in-line memory module with fault correction
#143Fully-buffered dual in-line memory module with fault correction
#144Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0
Dynamic random access memory device and associated refresh cycle
#146SHIELDED BITLINE ARCHITECTURE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARRAYS
#147Word line driver for DRAM embedded in a logic process
#148Semiconductor integrated circuit and data processing system
#149Semiconductor storage device and refresh control method therefor
#150Programmable memory and access method for the same
#151Memory system including nonvolatile memory and volatile memory and operating method of same
#152High performance tiling for RRAM memory
#153Controlling power consumption peaks in electronic circuits
#154Memory systems with column read to an arithmetic operation circuit, pattern detector circuits and methods and computer program products for the same
#155Scalable embedded DRAM array
#156Shielded bitline architecture for dynamic random access memory (DRAM) arrays
#157Semiconductor memory device, semiconductor integrated circuit system using the same, and control method of semiconductor memory device
#158Method and apparatus for synchronizing data from memory arrays
#159Transparent SDRAM in an embedded environment
#160Semiconductor device including a memory unit and a logic unit
#161Semiconductor Memory Device and Method of Operating the Same
#162Semiconductor memory device including a signal control device and method of operating the same
#163Active memory processing array topography and method
#164Ruined storage area marking and accessing method and system
#165Faulty storage area marking and accessing method and system
#166Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#167Word line driver for DRAM embedded in a logic process
#168Soft error protection in individual memory devices
#169Memory device
#170Integrated circuit test array including test module
#171Semiconductor integrated circuit
#172Dynamic RAM storage techniques
#173Semiconductor device and storage cell having multiple latch circuits
#174MEMORY DEVICE WITH SERIAL TRANSMISSION INTERFACE AND ERROR CORRECTION MEHTOD FOR SERIAL TRANSMISSION INTERFACE
#175Integrated circuit testing module including command driver
#176Method and system for performing system-level correction of memory errors
#177Memory having a portion that can be switched between use as data and use as error correction code (ECC)
#178Data storing method of dynamic RAM and semiconductor memory device
#179Synchronous semiconductor storage device having error correction function
#180Semiconductor memory device
#181Logic embedded memory having registers commonly used by macros
#182Method and system for controlling refresh to avoid memory cell data losses
#183Method and system for controlling refresh to avoid memory cell data losses
#184Method and system for controlling refresh to avoid memory cell data losses
#185Integrated circuit testing module
#186Semiconductor signal processing device
#187Microelectronic programmable device and methods of forming and programming the same
#188Semiconductor integrated circuit device in which a measure to counter soft errors is taken
#189Method and apparatus for protecting an integrated circuit from erroneous operation
#190Semiconductor memory and method for operating the same
#191Error correction in ROM embedded DRAM
#192Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture
#193Computer readable storage medium and semiconductor integrated circuit device
#194Method and system for controlling refresh to avoid memory cell data losses
#195Refresh-free dynamic semiconductor memory device
#196Error correction in ROM embedded DRAM
#197Error correction in ROM embedded DRAM
#198Error correction in ROM embedded DRAM
#199Bit refresh circuit for refreshing register bit values, integrated circuit device having the same, and method of refreshing register bit values
#200SRAM memory semiconductor integrated circuit device
#201Programmable structure, an array including the structure, and methods of forming the same
#202Error correction in ROM embedded DRAM
#203Semiconductor memory device
#204Programmable structure, an array including the structure, and methods of forming the same
#205Dynamic RAM storage techniques
#206Semiconductor integrated circuit adapted to output pass/fail results of internal operations
#207Dynamic random access memory having at least two buffer registers and method for controlling such a memory
#208Software power control of circuit modules in a shared and distributed DMA system
#209Semiconductor storage device and refresh control method therefor
#210Semiconductor integrated circuit device
#211Integrated circuit random access memory capable of automatic internal refresh of memory array
#212Semiconductor integrated circuit device having memory macros and logic cores on board
#213Concurrent refresh mode with distributed row address counters in an embedded DRAM
#214Scratchpad memory
#215Logical operation circuit and logical operation method
#216Memory system segmented power supply and control
#217High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
#218Memory circuit and method of generating the same
#219Semiconductor device
#220Semiconductor integrated circuit and data processing system
#221Magnetic memory devices having selective error encoding capability based on fault probabilities
#222Semiconductor device and testing apparatus for semiconductor device
#223Method for testing embedded DRAM arrays
#224Register file with a selectable keeper circuit
#225Method and apparatus for dynamically hiding a defect in an embedded memory
#226Low power consumption data input/output circuit of embedded memory device and data input/output method of the circuit
#227Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing
#228Semiconductor device having a thin film capacitor and method for fabricating the same
#229Method and system for supporting multiple cache configurations
#230Semiconductor memory including error correction function
#231Semiconductor device and method for testing the same
#232Low power circuits with small voltage swing transmission, voltage regeneration, and wide bandwidth architecture
#233Embedded electrically programmable read only memory devices
#234Multiple power levels for a chip within a multi-chip semiconductor package
#235Dynamic random access memory with smart refresh scheduler
#236Semiconductor memory apparatus and self-repair method
#237Multiple buffer memory interface
#238Configurable register circuitry for error detection and recovery