Semiconductor storage device

Semiconductor memory device and signal processing system

Hybrid parallel/serial bus interface

Memory system including a circuit to convert between parallel and serial bits

Multistage parallel-to-serial conversion of read data in memories, with the first serial bit skipping at least one stage

Semiconductor integrated circuit device

Semiconductor integrated circuit device having a common DRAM block accessed by a plurality of logic circuits

Memory array and method with simultaneous read/write capability

Semiconductor memory

Semiconductor memory

Semiconductor memory device for reducing address access time

Semiconductor memory device with late write function and data input/output method therefor

Memory device and method having data path with multiple prefetch I/O configurations

Memory device and method having data path with multiple prefetch I/O configurations

4N pre-fetch memory data transfer system

Apparatus and method for bidirectional transfer of data by a base station

Duty cycle distortion compensation for the data output of a memory device

Synchronous DRAM with selectable internal prefetch size

Cmos interface circuit

Data transfer apparatus for serial data transfer in system LSI

Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM

Write path scheme in synchronous DRAM

Method for writing data to a semiconductor memory comprising a peripheral circuit section and a memory core section including a memory cell

Scheme for optimal settings for DDR interface

Apparatuses, systems, and methods for data strobe write timing

Apparatuses and methods for providing clocks to data paths

Training and tracking of DDR memory interface strobe timing