199875 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells Memory devices with multiple cells per bit, e.g. twin-cells
TERNARY CONTENT ADDRESSABLE MEMORY AND DECISION GENERATION METHOD FOR THE SAME
#2APPARATUSES AND METHODS FOR OPERATIONS IN A SELF-REFRESH STATE
#3Content Addressable Memory Device Having Electrically Floating Body Transistor
#4MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGES
#5Ternary content addressable memory and decision generation method for the same
#6Bank selection for refreshing
#7Content addressable memory device having electrically floating body transistor
#8Apparatuses and methods for operations in a self-refresh state
#9Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages
#10Content addressable memory device having electrically floating body transistor
#11Ternary content addressable memory and decision generation method for the same
#12Apparatuses and methods for operations in a self-refresh state
#13Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages
#14CFET SRAM bit cell with two stacked device decks
#15Ternary content addressable memory and decision generation method for the same
#16Apparatuses and methods for cache operations
#17Content addressable memory device having electrically floating body transistor
#18Apparatuses and methods to change data category values
#19Content addressable memory device having electrically floating body transistor
#20Sensing a memory device
#21Apparatuses and methods to change data category values
#22Apparatuses and methods for cache operations
#23Apparatuses and methods for operations in a self-refresh state
#24Apparatuses and methods for concentrated arrangement of amplifiers
#25Apparatuses and methods to reverse data stored in memory
#26Apparatuses and methods to change data category values
#27Content addressable memory device having electrically floating body transistor
#28Complementary dual-modular redundancy memory cell
#29Apparatuses having memory strings compared to one another through a sense amplifier
#30Shifting data in sensing circuitry
#31Apparatuses and methods for concentrated arrangement of transistors of multiple amplifier circuits
#32Charge pump circuit with low reverse current and low peak current
#33Accessing data in memory
#34Apparatuses and methods including two transistor-one capacitor memory and for accessing same
#35Shifting data in sensing circuitry
#36Accessing data in memory
#37Content addressable memory device having electrically floating body transistor
#38Shifting data in sensing circuitry
#39Apparatuses and methods to reverse data stored in memory
#40Apparatuses and methods to change data category values
#41Apparatuses and methods including two transistor-one capacitor memory and for accessing same
#42Apparatuses and methods for operations in a self-refresh state
#43Charge pump circuit with low reverse current and low peak current
#44Apparatuses and methods for cache operations
#45Semiconductor device
#46Method of manufacturing a dual mode ferroelectric random access memory (FRAM) having imprinted read-only (RO) data
#47Apparatuses and methods to reverse data stored in memory
#48Error correction in differential memory devices with reading in single-ended mode in addition to reading in differential mode
#49Content addressable memory device having electrically floating body transistor
#50Hidden refresh method and operating method for pseudo SRAM
#51Low noise memory array
#52Implementing physically unclonable function (PUF) utilizing EDRAM memory cell capacitance variation
#53Morphing Memory Architecture
#54Phase change memory device
#55Memory with improved data reliability
#56Memory device
#57Phase change memory device
#58Mitigation of charge sharing in memory devices
#59Semiconductor memory device having variable-mode refresh operation
#60Twin cell architecture for integrated circuit dynamic random access memory (DRAM) devices and those devices incorporating embedded DRAM
#61SEMICONDUCTOR MEMORY DEVICE
#62Hierarchical 2T-DRAM with self-timed sensing
#63Semiconductor memory device
#64Semiconductor memory device
#65Hierarchical 2T-DRAM with self-timed sensing
#66Phase change memory device
#67Sense amplifier circuitry and architecture to write data into and/or read from memory cells
#68Device and method having a memory array storing each bit in multiple memory cells
#69Semiconductor memory device
#70Sense amplifier organization for twin cell memory devices
#71Semiconductor storage device
#72Low equalized sense-amp for twin cell DRAMs
#73Semiconductor memory device
#74Phase change memory device
#75Semiconductor memory device
#76Semiconductor memory device
#77Memory with selectable single cell or twin cell configuration
#78Sense amplifier circuitry and architecture to write data into and/or read from memory cells
#79Integrated DRAM memory device
#80Twin-cell bit line sensing configuration
#81Electronic memory with binary storage elements
#82Device and method having a memory array storing each bit in multiple memory cells
#83Refresh-free dynamic semiconductor memory device
#84Memory cell arrangement having dual memory cells
#85Semiconductor memory device having dummy word line
#86Flexible multi-area memory and electronic device using the same
#87FeRAM having differential data
#88Semiconductor memory device
#89FeRAM having test circuit and method for testing the same
#90Device having a memory array storing each bit in multiple memory cells
#91Semiconductor memory device with improved data retention characteristics
#92Semiconductor memory cell, array, architecture and device, and method of operating same