199879 ⎘
Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor; Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells; Refreshing of dynamic cells Parity or ECC in refresh operations
MEMORY DEVICE WITH DATA RETENTION CHARACTERISTICS AND OPERATING METHOD THEREOF
#2MAINTENANCE-BASED CONDITIONS FOR BLOCK RETIREMENT
#3APPARATUS WITH REFRESH MANAGEMENT MECHANISM
#4SEMICONDUCTOR MEMORY DEVICE-DIRECTED ERROR CHECK AND SCRUB
#5DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCE
#6APPARATUS WITH REFRESH MANAGEMENT MECHANISM
#7MEMORY DEVICE AND OPERATING METHOD THEREOF
#8Memory device interface and method
#9Memory device interface and method
#10Bank selection for refreshing
#11MEMORY BANK AND MEMORY
#12Trim level adjustments for memory based on data use
#13Semiconductor memory device
#14Apparatus with refresh management mechanism
#15METHODS AND APPARATUS FOR DYNAMICALLY ADJUSTING PERFORMANCE OF PARTITIONED MEMORY
#16Memory device interface and method
#17Semiconductor devices
#18Apparatus with combinational access mechanism and methods for operating the same
#19Apparatus with refresh management mechanism
#20Apparatus with combinational access mechanism and methods for operating the same
#21MEMORY DEVICE INTERFACE AND METHOD
#22Error correction methods and semiconductor devices and semiconductor systems using the same
#23Semiconductor devices
#24Semiconductor devices
#25Deferred error code correction with improved effective data bandwidth performance
#26Semiconductor devices
#27Memory device and multi physical cells error correction method thereof
#28Methods and apparatus for dynamically adjusting performance of partitioned memory
#29Error correction code scrub scheme
#30Deferred error code correction with improved effective data bandwidth performance
#31MEMORY DEVICE INTERFACE AND METHOD
#32Memory device interface and method
#33Semiconductor device and memory module including the semiconductor device for controlling a refresh cycle differently based on error correction code
#34Apparatus including refresh controller controlling refresh operation responsive to data error
#35Memory device detecting and correcting data error and operating method thereof
#36Electronic devices
#37Error correction code scrub scheme
#38Memory system for removing memory cell fault and method thereof
#39Memory device and operating method thereof
#40Memory systems and methods of controlling refresh operations of memory systems
#41Memory system and operating method thereof
#42Systems and methods for improved error correction in a refreshable memory
#43Refresh in memory based on monitor array threshold drift
#44Semiconductor device and method for controlling a refresh operation and a memory system including the same
#45Method of ECC encoding a DRAM and a DRAM
#46Refresh in memory based on a set margin
#47MEMORY SYSTEM AND OPERATION METHOD OF THE SAME
#48Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands
#49Semiconductor device and refresh rate control method of semiconductor device based on measured temperature
#50Dynamic Random Access Memory For Communications Systems
#51Semiconductor device and driving method thereof
#52Semiconductor system with a column control circuit
#53Method for memory scrub of DRAM with internal error correcting code (ECC) bits during either memory activate and/or precharge operation
#54Controller-based memory scrub for DRAMs with internal error-correcting code (ECC) bits contemporaneously during auto refresh or by using masked write commands
#55Method for scrubbing and correcting DRAM memory data with internal error-correcting code (ECC) bits contemporaneously during self-refresh state
#56Semiconductor device
#57Memory device
#58Memory device and operating method thereof
#59Semiconductor memory device having selective ECC function
#60Dynamic random access memory with configurable refresh rate for communications systems
#61Apparatus including refresh controller controlling refresh operation responsive to data error
#62Memory device having adjustable refresh period and method of operating the same
#63Memory system and method using partial ECC to achieve low power refresh and fast access to data
#64Apparatus, method and system to determine memory access command timing based on error detection
#65Dynamic random access memory for communications systems
#66Refresh rate performance based on in-system weak bit detection
#67Memory controller method and system compensating for memory cell data losses
#68Managing errors in a DRAM by weak cell encoding
#69Error Detection And Correction In A Memory System
#70Error Detection And Correction In A Memory System
#71Memory system and method using ECC with flag bit to identify modified data
#72Memory system and method using partial ECC to achieve low power refresh and fast access to data
#73Memory device having reconfigurable refresh timing
#74Digit line comparison circuits
#75Embedded DRAM having low power self-correction capability
#76Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
#77Semiconductor memory device with hidden refresh and method for controlling the same
#78Memory system and method using ECC with flag bit to identify modified data
#79Memory system and method using partial ECC to achieve low power refresh and fast access to data
#80Digit line comparison circuits
#81Error Correction in an Electronic Circuit
#82Memory controller method and system compensating for memory cell data losses
#83Semiconductor memory device capable of reducing current in PASR mode
#84SEMICONDUCTOR MEMORY DEVICE
#85Method and system for controlling refresh to avoid memory cell data losses
#86Systems, methods, and apparatuses to save memory self-refresh power
#87Memory device and refresh adjusting method
#88Semiconductor memory device and refresh period controlling method
#89Memory controller method and system compensating for memory cell data losses
#90Dynamic memory architecture employing passive expiration of data
#91Memory refresh system and method
#92Methods and apparatuses for refreshing non-volatile memory
#93Semiconductor memory device having an error correction function and associated method
#94Method and system for controlling refresh to avoid memory cell data losses
#95Semiconductor device and testing method for same
#96METHOD OF REFRESHING A DYNAMIC RANDOM ACCESS MEMORY AND CORRESPONDING DYNAMIC RANDOM ACCESS MEMORY DEVICE, IN PARTICULAR INCORPORATED INTO A CELLULAR MOBILE TELEPHONE
#97Memory system and method using ECC with flag bit to identify modified data
#98Memory system and method using partial ECC to achieve low power refresh and fast access to data
#99Method and system for controlling refresh to avoid memory cell data losses
#100Semiconductor storage device and refresh control method therefor
#101Parity-scanning and refresh in dynamic memory devices
#102DEVICE AND METHOD FOR REDUCING REFRESH CURRENT CONSUMPTION
#103Semiconductor storage device and refresh control method therefor
#104Semiconductor memory device having data holding mode using ECC function
#105Semiconductor integrated circuit device
#106Parity-scanning and refresh in dynamic memory devices
#107Memory having parity error correction
#108Memory having parity error correction
#109Data storing method of dynamic RAM and semiconductor memory device
#110Method and system for controlling refresh to avoid memory cell data losses
#111Method and system for controlling refresh to avoid memory cell data losses
#112Semiconductor storage device and pseudo SRAM
#113Method and system for controlling refresh to avoid memory cell data losses
#114Dynamic memory architecture employing passive expiration of data
#115Memory controller method and system compensating for memory cell data losses
#116Memory controller method and system compensating for memory cell data losses
#117Memory controller method and system compensating for memory cell data losses
#118Semiconductor memory and method for operating the same
#119Memory system and method using ECC to achieve low power refresh
#120Method and system for controlling refresh to avoid memory cell data losses
#121Refresh counter circuit and control method for refresh operation
#122Semiconductor memory device
#123Semiconductor memory device
#124Semiconductor memory device and refresh period controlling method
#125Memory controller method and system compensating for memory cell data losses
#126Semiconductor device and testing method for same
#127Semiconductor storage device and refresh control method therefor
#128Parity-scanning and refresh in dynamic memory devices
#129Semiconductor integrated circuit device and error checking and correcting method thereof
#130Methods and apparatus for dynamically adjusting performance of partitioned memory
#131Dynamic adjustment of refresh rate