199768 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing; Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details; Address generation devices; Devices for accessing memories, e.g. details of addressing circuits Accessing multiple arrays
Sub-classes:MEMORY MODULE REGISTER ACCESS
#2Method and Apparatus for Processing Page Fault in Memory Access
#3NON-VOLATILE MEMORY AND REWRITE CONTROL METHOD THEREOF
#4Memory module register access
#5APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA
#6At-speed test of functional memory interface logic in devices
#7Memory module register access
#8Die-based high and low priority error queues
#9Memory management device, system and method
#10Die-based high and low priority error queues
#11DETERMINATION OF A MATCH BETWEEN DATA VALUES STORED BY THREE OR MORE ARRAYS
#12AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
#13Memory module register access
#14Configurable trim settings on a memory device
#15Memory management device, system and method
#16Multiple algorithmic pattern generator testing of a memory device
#17Hamming-distance analyzer and method for analyzing hamming-distance
#18Semiconductor device, memory test method for semiconductor device, and test pattern generation program
#19Integrated characterization vehicles for non-volatile memory cells
#20Determination of a match between data values stored by three or more arrays
#21Memory devices and memory packages
#22Content addressable memory with match hit quality indication
#23Inspection apparatus, image sensing apparatus, electronic equipment, and transportation equipment
#24Memory module register access
#25Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths
#26Configurable trim settings on a memory device
#27Byte enable memory built-in self-test (MBIST) algorithm
#28Multi-processor core device with MBIST
#29Memory Module and Memory System
#30Semiconductor memory device
#31Built-in-self-test circuits and methods using pipeline registers
#32SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY AND METHOD FOR TESTING RELIABILITY OF SEMICONDUCTOR DEVICE
#33Parallel memory self-testing
#34Hamming-distance analyzer and method for analyzing hamming-distance
#35Memory module and memory system
#36Semiconductor device and diagnostic method therefor
#37Content addressable memory with match hit quality indication
#38Semiconductor device and semiconductor integrated system
#39Fail bit counter and semiconductor memory device having the same
#40Memory device including a redundancy column and a redundancy peripheral logic circuit
#41Background reference positioning and local reference positioning using threshold voltage shift read
#42Nonvolatile memory system with background reference positioning and local reference positioning
#43Semiconductor device using a parallel bit operation and method of operating the same
#44Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion
#45Stack type semiconductor memory and semiconductor system using the same
#46Fast soft data by detecting leakage current and sensing time
#47Semiconductor memory and semiconductor system using the same
#48Memory test system and method of testing memory device
#49Nonvolatile memory device detecting defective bit line at high speed and test system thereof
#50Three-dimensional flash memory system
#51Arithmetic processing device storing diagnostic results in parallel with diagnosing, information processing apparatus and control method of arithmetic processing device
#52Semiconductor apparatus
#53Memory module register access
#54Semiconductor memory apparatus
#55Memory device reducing test time and computing system including the same
#56Circuit for testing integrated circuits
#57Memory device and method for testing reliability of memory device
#58Method and apparatus for testing memory
#59Test system simultaneously testing semiconductor devices
#60Power-aware memory self-test unit
#61Non-volatile memory with multi-word line select for defect detection operations
#62Method and apparatus for multiple memory shared collar architecture
#63Memory block quality identification in a memory
#64Operating method of memory controller and nonvolatile memory device
#65Memory module having address mirroring function
#66Memory device, memory system, and method for operating memory device
#67Bad memory unit detection in a solid state drive
#68Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths
#69Semiconductor device for parallel bit test and test method thereof
#70Word line test control circuit of semiconductor apparatus and testing method thereof
#71Failure diagnosis circuit
#72Semiconductor integrated circuit device and multi chip package including the same
#73Partial chip, and systems having the same
#74Detecting missing write to cache/memory operations
#75Method for performing built-in self-tests
#76Memory test system and method
#77Device and method to perform a parallel memory test
#78Semiconductor memory device
#79Semiconductor device
#80Memory module and memory system
#81Semiconductor device and test method thereof
#82Integrated circuit chip and multi-chip system including the same
#83Methods and apparatuses for stacked device testing
#84Systems and methods for testing pages of data stored in a memory module
#85Memory testing of three dimensional (3D) stacked memory
#86Semiconductor apparatus, test method using the same and muti chips system
#87Semiconductor device
#88Three-dimensional flash memory system
#89Semiconductor memory device
#90Semiconductor device and test method thereof
#91Resistive memory device
#92Implementing timing alignment and synchronized memory activities of multiple memory devices accessed in parallel
#933-D memory and built-in self-test circuit thereof
#94Permutational memory cells
#95Semiconductor device and semiconductor system including the same
#96Tree based adaptive die enumeration
#97Memory system and test method thereof
#98Functional screening of static random access memories using an array bias voltage
#99Fabrication and testing method for nonvolatile memory devices
#100Control scheme for 3D memory IC
#101Solid-state disk manufacturing self test
#102Failure diagnosis circuit
#103Semiconductor integrated circuit
#104Fully-buffered dual in-line memory module with fault correction
#105Memory device and method for driving memory device
#106Multi-test apparatus and method for testing a plurailty of semiconductor chips
#107Memory and test method for memory
#108Memory module and memory system
#109Semiconductor apparatus
#110Semiconductor memory device
#111Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces
#112Multi-chip package and method of operating the same
#113MEMORY BUILT-IN SELF TEST SCHEME FOR CONTENT ADDRESSABLE MEMORY ARRAY
#114METHOD AND APPARATUS FOR PERFORMING A MEMORY BUILT-IN SELF-TEST ON A PLURALITY OF MEMORY ELEMENT ARRAYS
#115Apparatus and methods for testing writability and readability of memory cell arrays
#116Semiconductor device and test method thereof
#117System and method for testing integrated circuits
#118DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE
#119Circuit for testing integrated circuits
#120Memory module including parallel test apparatus
#121Multi-Bank Read/Write To Reduce Test-Time In Memories
#122Method and apparatus for testing high capacity/high bandwidth memory devices
#123Hybrid self-test circuit structure
#124Memory module and memory system
#125SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT
#126Semiconductor device including first semiconductor chip including first pads connected to first terminals, and second semiconductor chip including second pads connected to second terminals
#127Multi-bit test control circuit
#128Fully-buffered dual in-line memory module with fault correction
#129Fully-buffered dual in-line memory module with fault correction
#130Multi-port memory device
#131Semiconductor memory apparatus
#132Memory-daughter-card-testing method and apparatus
#133Method and device for bad-block testing
#134Multi-port semiconductor memory device having variable access paths and method therefor
#135Multi-port memory device with serial input/output interface
#136Circuit and method for parallel testing and semiconductor device
#137Defective memory block identification in a memory device
#138Transport subsystem for an MBIST chain architecture
#139Method and apparatus for testing high capacity/high bandwidth memory devices
#140Apparatus for writing to multiple banks of a memory device
#141Test circuit for multi-port memory device
#142Test system for conducting parallel bit test
#143Memory module and memory device
#144Semiconductor memory device and semiconductor memory device test method
#145MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR
#146Microprocessor memory management
#147Apparatus and method for adjusting a supply voltage based on a read result
#148Semiconductor memory device and method for testing the same
#149Semiconductor device with a plurality of ground planes
#150Histogram generation with banks for improved memory access performance
#151Semiconductor memory capable of testing a failure before programming a fuse circuit and method thereof
#152Method of testing data paths in an electronic circuit
#153Memory apparatus which provides notification of memory capacity
#154Test circuit and method for use in semiconductor memory device
#155Semiconductor memory device
#156Semiconductor device and method of testing semiconductor device
#157Multi-port semiconductor memory device
#158Parallel bit test apparatus and parallel bit test method capable of reducing test time
#159PARALLEL READ FOR FRONT END COMPRESSION MODE
#160Flash EEPROM System
#161Method and apparatus for testing a memory chip using a common node for multiple inputs and outputs
#162Memory with improved BIST
#163Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces
#164Memory bus output driver of a multi-bank memory device and method therefor
#165Memory module and memory device
#166Semiconductor memory device having advanced test mode
#167Semiconductor memory device and data write and read method thereof
#168System and method for testing memory blocks in an SOC design
#169Multi-port memory device
#170Semiconductor apparatus and testing method
#171Memory-daughter-card-testing apparatus and method
#172Method for testing memory device
#173Semiconductor integrated circuit and BIST circuit design method
#174Daisy chainable memory chip
#175Daisy chainable memory chip
#176Memory device, and method for operating a memory device
#177Multi-port memory device with serial input/output interface
#178Method and system for improving reliability of memory device
#179Independent polling for multi-page programming
#180Method for writing to multiple banks of a memory device
#181Semiconductor device with a relief processing portion
#182Semiconductor memory device to which test data is written
#183Independent polling for multi-page programming
#184Semiconductor memory device
#185Memory built in self test circuit and method for generating a hardware circuit comprising the routing boxes thereof
#186Semiconductor memory apparatus having noise generating block and method of testing the same
#187Multi-port memory device with serial input/output interface and control method thereof
#188Semiconductor memory device
#189Semiconductor storage device
#190Multiple banks read and data compression for back end test
#191Parallel read for front end compression mode
#192Apparatus for controlling test mode of semiconductor memory
#193Semiconductor integrated circuit and testing method thereof
#194Apparatus and method for dynamically repairing a semiconductor memory
#195Memory block quality identification in a memory device
#196Fully-buffered dual in-line memory module with fault correction
#197Fully-buffered dual in-line memory module with fault correction
#198Fully-buffered dual in-line memory module with fault correction
#199Apparatus and method for reducing test resources in testing drams
#200Fully-buffered dual in-line memory module with fault correction
#201Multi-port semiconductor memory device having variable access paths and method
#202Semiconductor memory device
#203Apparatus and method for testing removable flash memory devices
#204Scratch control memory array in a flash memory device
#205Testing a multibank memory module
#206Test circuit for multi-port memory device
#207Multi-port semiconductor memory device
#208Method for testing memory device
#209Nonvolatile semiconductor memory device having redundant relief technique
#210Integrated circuit, test system and method for reading out an error datum from the integrated circuit
#211Memory module and memory system
#212Handling defective memory blocks of NAND memory devices
#213Multiple erase block tagging in a flash memory device
#214Defective memory block identification in a memory device
#215Memory block quality identification in a memory device
#216Semiconductor memory device and testing method thereof
#217Area efficient BIST system for memories
#218Integrated circuit with a control input that can be disabled
#219Integrated circuit and method for testing memory on the integrated circuit
#220Memory reliability detection system and method
#221Scratch control memory array in a flash memory device
#222Semiconductor memory device
#223System and method of testing a plurality of memory blocks of an integrated circuit in parallel
#224Method and BIST architecture for fast memory testing in platform-based integrated circuit
#225Memory buffer
#226Memory block quality identification in a memory device
#227Semiconductor device
#228Memory cell test circuit for use in semiconductor memory device and its method
#229Method of testing memory module and memory module
#230Defective memory block identification in a memory device
#231Apparatus for dynamically repairing a semiconductor memory
#232Method for testing a memory device and memory device for carrying out the method
#233Built-in self test systems and methods for multiple memories
#234Handling defective memory blocks of NAND memory devices
#235Flash EEprom system
#236Semi-conductor component test procedure, in particular for a system with several modules, each comprising a data buffer component, as well as a test module to be used in a corresponding procedure
#237Apparatus and method for reducing test resources in testing DRAMs
#238Semi-conductor component test procedure, as well as a data buffer component
#239Multi-port memory device having serial I/O interface
#240Integrated module having a plurality of separate substrates
#241Memory card apparatus configured to provide notification of memory capacity
#242Semiconductor device with a plurality of ground planes
#243Semiconductor memory device and test method thereof
#244Multiple-select multiplexer circuit, semiconductor memory device including a multiplexer circuit and method of testing the semiconductor memory device
#245Bank selectable parallel test circuit and parallel test method thereof
#246Semiconductor memory device and method of testing semiconductor memory device
#247Semiconductor memory device having advanced test mode
#248Semiconductor device for detecting memory failure and method thereof
#249RAM memory circuit having a plurality of banks and an auxiliary device for testing
#250Random access memory using precharge timers in test mode
#251Semiconductor storage device formed to optimize test technique and redundancy technology
#252Semiconductor device and testing circuit which can carries out a verifying test effectively for non-volatile memory cells
#253System for optimizing anti-fuse repair time using fuse id
#254Method for testing embedded DRAM arrays
#255Apparatus and method for dynamically repairing a semiconductor memory
#256Distributed memory initialization and test methods and apparatus
#257FeRAM having test circuit and method for testing the same
#258Integrated memory having a test circuit for functional testing of the memory
#259Multiple erase block tagging in a flash memory device
#260Simultaneous and selective memory macro testing
#261Refresh time detection circuit and semiconductor device including the same
#262Decoding data using bit line defect information