199789 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals; Marginal testing, e.g. race, voltage or current testing of timing
Latency detection in a memory built-in self-test by using a ping signal
#302Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logic
#303Memory controller and memory control method
#304Semiconductor memory device and method of testing the same
#305System and method for on-board timing margin testing of memory modules
#306Method and system for measuring memory access time using phase detector
#307Apparatus and method for trimming static delay of a synchronizing circuit
#308METHOD FOR DETERMINING QUALITY PARAMETER AND THE ELECTRONIC APPARATUS USING THE SAME
#309Semiconductor device, internal circuit control signal measurement circuit, and delay time measurement method
#310Variable-loop-path ring oscillator test circuit and systems and methods utilizing same
#311Data processing apparatus
#312Methods And Apparatus For Testing Electronic Circuits
#313METHOD FOR DETECTING MEMORY TRAINING RESULT AND COMPUTER SYSTEM USING SUCH METHOD
#314Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift
#315Interface for writing to memories having different write times
#316Drift tracking feedback for communication channels
#317Delay-lock loop and method adapting itself to operate over a wide frequency range
#318METHOD FOR AT-SPEED TESTING OF MEMORY INTERFACE USING SCAN
#319Semiconductor integrated circuit device for controlling a sense amplifier
#320Memory test circuit which tests address access time of clock synchronized memory
#321Semiconductor memory device for controlling banks
#322Apparatus for measuring data setup/hold time
#323Memory operation testing
#324Write latency tracking using a delay lock loop in a synchronous DRAM
#325Data transfer circuit and semiconductor memory device including the same
#326SMI memory read data capture margin characterization circuits and methods
#327System and method for an asynchronous data buffer having buffer write and read pointers
#328System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices
#329DDR memory controller
#330Programmable pulsewidth and delay generating circuit for integrated circuits
#331Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
#332Memory block testing
#333Simulating a memory circuit
#334High-speed testing of integrated devices
#335METHODS AND COMPUTER PROGRAM PRODUCTS FOR DETERMINING SIMULTANEOUS SWITCHING INDUCED DATA OUTPUT TIMING SKEW
#336Sensing delay circuit and semiconductor memory device using the same
#337Technique for determining performance characteristics of electronic devices and systems
#338Integrated circuits with programmable well biasing
#339Asynchronous, high-bandwidth memory component using calibrated timing elements
#340Semiconductor device having transmission control circuit
#341Apparatus for testing memory device
#342Method and apparatus for memory AC timing measurement
#343Adapting word line pulse widths in memory systems
#344Memory including a performance test circuit
#345Method and apparatus for signaling between devices of a memory system
#346Apparatus, memory device and method of improving redundancy
#347METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE
#348Memory system and data transmission method
#349Storage array including a local clock buffer with programmable timing
#350Semiconductor integrated circuit and electronic device
#351Test method and semiconductor device
#352Integrated circuits with programmable well biasing
#353Method for recording memory parameter and method for optimizing memory
#354Delay stage-interweaved analog DLL/PLL
#355Memory module with termination component
#356SEMICONDUCTOR INTEGRATED CIRCUIT
#357Output controller capable of generating only necessary control signals based on an activated selection signal
#358Speedpath repair in an integrated circuit
#359Memory device and testing with write completion detection
#360SAMPLING CIRCUIT AND METHOD
#361Wordline-to-bitline output timing ring oscillator circuit for evaluating storage array performance
#362Method and apparatus for improving data transfer
#363Oscillation device, method of oscillation, and memory device
#364Memory system and semiconductor integrated circuit
#365Local skew detecting circuit for semiconductor memory apparatus
#366Power supply voltage detection circuit and semiconductor integrated circuit device
#367Method for improving stability and lock time for synchronous circuits
#368Method, Device And Computer Program For Evaluating A Signal Transmission
#369Programmable pulsewidth and delay generating circuit for integrated circuits
#370Semiconductor memory device and test method therefor
#371Semiconductor device with self refresh test mode
#372Storage cell design evaluation circuit including a wordline timing and cell access detection circuit
#373Semiconductor memory device and control method thereof
#374Methods and apparatus for testing delay locked loops and clock skew
#375Systems, modules, chips, circuits and methods with delay trim value updates on power-up
#376Method for checking the integrity of a clock tree
#377Semiconductor memory apparatus with write training function
#378System and method for controlling timing of output signals
#379Over temperature detection apparatus and method thereof
#380CIRCUIT MEASURING OPERATING SPEED AND RELATED SEMICONDUCTOR MEMORY DEVICE
#381Semiconductor memory device and defect remedying method thereof
#382Calibration circuit of a semiconductor memory device and method of operating the same
#383On-chip self test circuit and self test method for signal distortion
#384Built-in system and method for testing integrated circuit timing parameters
#385Multi-component module fly-by output alignment arrangement and method
#386Write latency tracking using a delay lock loop in a synchronous DRAM
#387Semiconductor memory and operating method of same
#388Semiconductor memory device with various delay values
#389Test structure for characterizing multi-port static random access memory and register file arrays
#390Delayed sense amplifier multiplexer isolation
#391Asynchronous, high-bandwidth memory component using calibrated timing elements
#392Apparatus and method for adjusting slew rate in semiconductor memory device
#393METHOD OF TESTING MEMORY DEVICE
#394Method for evaluating storage cell design using a wordline timing and cell access detection circuit
#395Data training system and method thereof
#396Method for evaluating memory cell performance
#397Data capture window synchronizing method for generating data bit sequences and adjusting capture window on parallel data paths
#398Adaptive memory calibration using bins
#399Method of output slew rate control
#400TRAINING OF SIGNAL TRANSFER CHANNELS BETWEEN MEMORY CONTROLLER AND MEMORY DEVICE
#401System having a controller device, a buffer device and a plurality of memory devices
#402Method for automatic adjustment of timing of double data rate interface
#403Method of timing calibration using slower data rate pattern
#404Ring oscillator row circuit for evaluating memory cell performance
#405Semiconductor memory device
#406Memory accessing circuit system
#407CIRCUITRY FOR RELIABILITY TESTING AS A FUNCTION OF SLEW
#408Memory write timing system
#409Phase shift adjusting method and circuit
#410Semiconductor memory and testing method of same
#411System and method for asynchronous clock regeneration
#412INTEGRATED CIRCUIT FOR MEASURING SET-UP AND HOLD TIMES FOR A LATCH ELEMENT
#413METHOD OF FIXING A READ EVALUATION TIME OR THE DIFFERENCE BETWEEN A READ CHARGE VOLTAGE AND A READ DISCRIMINATING VOLTAGE IN A NON-VOLATILE NAND TYPE MEMORY DEVICE
#414Method and device for verifying output signals of an integrated circuit
#415Semiconductor memory device
#416Semiconductor memory device and semiconductor device comprising the same
#417Buffered memory having a control bus and dedicated data lines
#418System and method for simulating an aspect of a memory circuit
#419System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
#420Semiconductor device
#421Memory systems and memory modules
#422Synchronous memory read data capture
#423Semiconductor memory apparatus having plurality of sense amplifier arrays having different activation timing
#424Measuring circuit for qualifying a memory located on a semiconductor device
#425Semiconductor integrated circuit and a method of testing the same
#426Independent polling for multi-page programming
#427Methods and apparatus for testing delay locked loops and clock skew
#428Methods and devices for regulating the timing of control signals in integrated circuit memory devices
#429Built-in system and method for testing integrated circuit timing parameters
#430Apparatus for controlling activation period of word line of volatile memory device and method thereof
#431Memory system and semiconductor integrated circuit
#432Semiconductor Memory
#433Dll Circuit
#434Method for at-speed testing of memory interface using scan
#435Memory block testing
#436Speed adjustment system and method for performing the same
#437Methods and apparatus for inline characterization of high speed operating margins of a storage element
#438Independent polling for multi-page programming
#439Serial bus controller using nonvolatile ferroelectric memory
#440Measuring apparatus, measuring method, testing apparatus, testing method, and electronic device
#441Dft Technique for Stressing Self-Timed Semiconductor Memories to Detect Delay Faults
#442Semiconductor integrated circuit and electronic device
#443Memory controller device having timing offset capability
#444Semiconductor integrated circuit and testing method for the same
#445Semiconductor apparatus and test method therefor
#446Semiconductor memory device and defect remedying method thereof
#447Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance
#448Integrated Semiconductor Memory and Methods for Testing and Operating the Same
#449Device and method for testing memory access time using PLL
#450Die based trimming
#451Circuit and method for adjusting threshold drift over temperature in a CMOS receiver
#452Drift tracking feedback for communication channels
#453Programmable delay introducing circuit in self timed memory
#454Memory module
#455Semiconductor integrated circuit and test system for testing the same
#456Delay-locked loop, integrated circuit having the same, and method of driving the same
#457Setting threshold voltages of cells in a memory block to reduce leakage in the memory block
#458Write latency tracking using a delay lock loop in a synchronous DRAM
#459Method and apparatus for an oscillator within a memory device
#460Data input method and apparatus, and liquid crystal display device using the same
#461Apparatus and method for trimming static delay of a synchronizing circuit
#462Data invalid signal for non-deterministic latency in a memory system
#463Configurable MRAM and method of configuration
#464Data input circuit of semiconductor memory device and data input method thereof
#465Apparatus and method for controlling enable time of signal controlling operation of data buses of memory device
#466Precharge apparatus
#467Semiconductor memory device having delay circuit
#468Systems and methods for automatically eliminating imbalance between signals
#469System and method for controlling timing of output signals
#470Drift tracking feedback for communication channels
#471Row circuit ring oscillator method for evaluating memory cell performance
#472Semiconductor integrated circuit apparatus and interface test method
#473Method of reducing disturbs in non-volatile memory
#474Output controller with test unit
#475Output controller for controlling data output of a synchronous semiconductor memory device
#476Method for generating adjustable MRAM timing signals
#477Test mode method and apparatus for internal memory timing signals
#478Semiconductor device
#479Memory system and data transmission method
#480Semiconductor integrated circuit device
#481Interface circuit
#482Methods and apparatus for testing electronic circuits
#483Integrated memory core and memory interface circuit
#484Semiconductor device, testing and manufacturing methods thereof
#485Interface circuit and semiconductor device
#486System and method for injecting phase jitter into integrated circuit test signals
#487Apparatus and method for testing circuit characteristics by using eye mask
#488Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies
#489Integrated scannable interface for testing memory
#490Delay-lock loop and method adapting itself to operate over a wide frequency range
#491Circuitry and method for adjusting signal length
#492DQS strobe centering (data eye training) method
#493Method for improving stability and lock time for synchronous circuits
#494Semiconductor integrated circuit device
#495Semiconductor memory
#496Test mode for programming rate and precharge time for DRAM activate-precharge cycle
#497Delay-lock loop and method adapting itself to operate over a wide frequency range
#498Regulating a timing between a strobe signal and a data signal
#499Memory device and method having a data bypass path to allow rapid testing and calibration
#500Test apparatus and test method
#501Memory system and semiconductor integrated circuit
#502System and method for reducing jitter of signals coupled through adjacent signal lines
#503Integrated circuit margin stress test system
#504System and method for on-board timing margin testing of memory modules
#505System and method for an asynchronous data buffer having buffer write and read pointers
#506Circuits and methods for controlling timing skew in semiconductor memory devices
#507Data strobe synchronization for DRAM devices
#508Synchronous output buffer, synchronous memory device and method of testing access time
#509Semiconductor memory device and memory system using same
#510Daisy chained multi-device system and operating method
#511Device and method for pulse width control in a phase change memory device
#512System and method for providing on-chip clock generation verification using an external clock
#513Apparatus for controlling activation period of word line of volatile memory device and method thereof
#514System, method and storage medium for providing programmable delay chains for a memory system
#515Serial bus controller using nonvolatile ferroelectric memory
#516Semiconductor component test procedure, as well as a data buffer component
#517Duty cycle detector with first, second, and third values
#518On-chip self test circuit and self test method for signal distortion
#519Semiconductor device having a mode of functional test
#520System and method for testing differential signal crossover using undersampling
#521Calibration circuit of a semiconductor memory device and method of operating the same
#522Apparatus and method for latency control in high frequency synchronous semiconductor device
#523Test method, control circuit and system for reduced time combined write window and retention testing
#524Technique for determining performance characteristics of electronic devices and systems
#525Test validation of an integrated device
#526Method, system and memory controller utilizing adjustable read data delay settings
#527Integrated circuit device having a test circuit to measure AC characteristics of internal memory macro
#528Semiconductor integrated circuit and a method of testing the same
#529Semiconductor memory device and defect remedying method thereof
#530Method and apparatus for optimizing strobe to clock relationship
#531Robust and high-speed memory access with adaptive interface timing
#532Methods for determining simultaneous switching induced data output timing skew
#533Delay stage-interweaved analog DLL/PLL
#534Delay stage-interweaved analog DLL/PLL
#535Delay stage-interweaved analog DLL/PLL
#536Latency control circuit and method of latency control
#537Semiconductor memory device with adjustable I/O bandwidth
#538Method, system and memory controller utilizing adjustable write data delay settings
#539Integrated circuit buffer device
#540Self test for the phase angle of the data read clock signal DQS
#541Data training in memory device
#542Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods
#543Loop-back method for measuring the interface timing of semiconductor memory devices using the normal mode memory
#544Circuit for verifying the write speed of SRAM cells
#545Method for routing data paths in a semiconductor chip with a plurality of layers
#546Test apparatus, phase adjusting method and memory controller
#547Method and apparatus for encoding memory control signals to reduce pin count
#548Memory module with termination component
#549Drift tracking feedback for communication channels
#550Clock-synchronous semiconductor memory device
#551Delay stage-interweaved analog DLL/PLL
#552Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
#553Semiconductor memory
#554Method of reducing disturbs in non-volatile memory
#555Memory system having fast and slow data reading mechanisms
#556Refresh-free dynamic semiconductor memory device
#557Memory module with termination component
#558Circuit and method for adjusting threshold drift over temperature in a CMOS receiver
#559Internal signal test device and method thereof
#560System and method for an asynchronous data buffer having buffer write and read pointers
#561Adjustable timing circuit of an integrated circuit
#562Circuits and methods of temperature compensation for refresh oscillator
#563Circuits and methods of temperature compensation for refresh oscillator
#564Multi-chip packaged integrated circuit device for transmitting signals from one chip to another chip
#565Semiconductor memory device
#566Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit
#567Semiconductor device with self refresh test mode
#568Adjustable timing circuit of an integrated circuit
#569Semi-conductor component test procedure, as well as a data buffer component
#570Method for detecting column fail by controlling sense amplifier of memory device
#571Memory device having delay locked loop
#572Method for testing an integrated semiconductor memory
#573Semiconductor device with self refresh test mode
#574Asynchronous, high-bandwidth memory component using calibrated timing elements
#575Semiconductor memory device having a delay circuit
#576Apparatus and method for adjusting slew rate in semiconductor memory device
#577Method and apparatus for detecting array degradation and logic degradation
#578Integrated circuit
#579Delay detecting apparatus of delay element in semiconductor device and method thereof
#580Buffer device and method of operation in a buffer device
#581Method for testing an integrated semiconductor memory with a shortened reading time
#582Method for detecting resistive-open defects in semiconductor memories
#583Electrical fuse control of memory slowdown
#584Circuit for controlling an enabling time of an internal control signal according to an operating frequency of a memory device and the method thereof
#585Drift tracking feedback for communication channels
#586Memory module having an integrated circuit buffer device
#587System having a controller device, a buffer device and a plurality of memory devices
#588Method of timing calibration using slower data rate pattern
#589Apparatus for determining the access time and/or the minimally allowable cycle time of a memory
#590Method and apparatus for optimizing timing for a multi-drop bus
#591Semiconductor device capable of performing test at actual operating frequency
#592Integrated circuit buffer device
#593Semiconductor memory device having test mode for data access time
#594Semiconductor memory device and defect remedying method thereof
#595Semiconductor memory module, memory system, circuit, semiconductor device, and DIMM
#596Apparatus and method for controlling enable time of signal controlling operation of data buses of memory device
#597Memory device with clock multiplier circuit
#598Configurable width buffered module having switch elements
#599Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
#600Providing memory test patterns for DLL calibration