VOTING-BASED STATE SELECTION FOR A VOLATILE MEMORY

MEMORY DEVICE WITH REDUNDANCY FOR PAGE-BASED REPAIR

MEMORY DEVICE INCLUDING CALIBRATION OPERATION AND TRANSISTOR HAVING ADJUSTABLE THRESHOLD VOLTAGE

MEMORY DEVICE AND METHOD OF TESTING THE MEMORY DEVICE FOR FAILURE

SENSE AMPLIFIER AND OUTPUT LATCH CIRCUIT FOR TESTING

Reliable Programming of One-Time Programmable (OTP) Memory During Device Testing

SEMICONDUCTOR DEVICE RELATED TO A PARALLEL TEST

SIGNAL QUALITY OPTIMIZATION METHOD AND A SIGNAL QUALITY OPTIMIZATION SYSTEM

Memory device with redundancy for page-based repair

MEMORY CHIP

TECHNIQUES TO ALLOCATE MEMORY FOR IN-LINE OR IN-BAND ERROR CORRECTION CONTROL

Semiconductor device and retention test method

Memory device and method of testing the memory device for failure

Memory device with redundancy for page-based repair

Asynchronous signal to command timing calibration for testing accuracy

Configurable scan chain architecture for multi-port memory

Built-in high-frequency test circuitry without duty distortion

DEVICE AND METHOD FOR TESTING FATIGUE CHARACTERISTICS OF SELECTOR

Method and apparatus for testing memory, medium and device

TRANSFORMING LOCAL WIRE THRU RESISTANCES INTO GLOBAL DISTRIBUTED RESISTANCES

METHOD AND DEVICE FOR TESTING MEMORY

Simulating memory cell sensing for testing sensing circuitry

Reference bits test and repair using memory built-in self-test

Memory device performing repair operation

Semiconductor device including a memory management unit

Nonvolatile memory device and storage device including nonvolatile memory device

TEST METHOD AND TEST SYSTEM

STACKED MEMORY DEVICE AND TEST METHOD THEREOF

Semiconductor device

Memory device including calibration operation and transistor having adjustable threshold voltage

Insulated gate bipolar transistor physical model

Digital circuit testing and analysis module, system and method thereof

Address generators for verifying integrated circuit hardware designs for cache memory

Test program generation method, device, memory medium and electronic equipment

On-die memory power analytics and management

Address generators for verifying integrated circuit hardware designs for cache memory

Semiconductor integrated circuit

Automatic test-pattern generation for memory-shadow-logic testing

Persistent command parameter table for pre-silicon device testing

Delayed equivalence identification

Semiconductor device using a parallel bit operation and method of operating the same

Systems and methods for analyzing soft errors in a design and reducing the associated failure rates thereof

Low power VLSI designs using circuit failure in sequential cells as low voltage check for limit of operation

Test mode setting circuit and semiconductor device including the same

Persistent command parameter table for pre-silicon device testing

Implementing hidden security key in eFuses

Implementing hidden security key in eFuses

Design-for-test apparatuses and techniques

Impedance calibration circuit, and semiconductor memory and memory system using the same

System and method for simulating a memory technology

Stacked semiconductor apparatus and semiconductor system capable of inputting signals through various paths

Physical memory fault mitigation in a computing environment

Automatic test-pattern generation for memory-shadow-logic testing

Method for performing memory interface calibration in an electronic device, and associated apparatus and associated memory controller

Write pulse width scheme in a resistive memory

Physical memory fault mitigation in a computing environment

Error generating apparatus for solid state drive tester

Built-in-self-test (BIST) organizational file generation

Integrated circuit chip and memory device

SRAM timing tracking circuit

Automatic test-pattern generation for memory-shadow-logic testing

Universal test structures based SRAM on-chip parametric test module and methods of operating and testing

Defective-ratio predicting method, defective-ratio predicting program, managing method for semiconductor manufacturing apparatus, and manufacturing method for semiconductor device

Semiconductor integrated circuit, design support software system, and automatic test pattern generation system

Design Structure for a Circuit and Method to Measure Threshold Voltage Distributions in SRAM Devices

Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers

SYSTEM AND COMPUTER PROGRAM FOR EFFICIENT CELL FAILURE RATE ESTIMATION IN CELL ARRAYS

Memory device testable without using data and dataless test method

Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering

Real-time optimized testing of semiconductor device

Method and computer program for efficient cell failure rate estimation in cell arrays

Semiconductor integrated circuit, design support software system and automatic test pattern generation system

Efficient modeling of embedded memories in bounded memory checking

System and method for testing a memory

Method for localization and generation of short critical sequence

Testing MEM device array

Memory channel self test

[INTEGRATED CIRCUIT AND METHOD FOR SIMULATING AND TRIMMING THEREOF]

Semiconductor integrated circuit verification system

Reliable electronic fuse based storage using error correction coding

Method for testing memory device and test system

Automatic built-in self test for memory arrays