199807 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
REDUNDANCY TECHNIQUES FOR MULTI-CHANNEL MEMORY DEVICES
#23D STACKED INTEGRATED CIRCUITS HAVING FUNCTIONAL BLOCKS CONFIGURED TO PROVIDE REDUNDANCY SITES
#33D stacked integrated circuits having functional blocks configured to provide redundancy sites
#43D stacked integrated circuits having functional blocks configured to provide redundancy sites
#5Runtime cell row replacement in a memory
#6Storage device and method of operating the same
#7Redundant array of independent NAND for a three-dimensional memory array
#8Apparatus and method for storing data in an MLC area of a memory system
#93D stacked integrated circuits having functional blocks configured to provide redundancy sites
#10Memory dispatcher
#113D stacked integrated circuits having functional blocks configured to provide redundancy sites
#12Using dual channel memory as single channel memory with spares
#13Single and double chip spare
#14Reading of start-up information from different memory regions of a memory system
#15Redundant array of independent NAND for a three-dimensional memory array
#16Memory with an error correction function and related memory system
#17Internal copy to handle NAND program fail
#18Memory event mitigation in redundant software installations
#19Techniques to store data for critical chunk operations
#20Storage system, computing system, and methods thereof
#21Storage Device and Data Control Method for Storage Error Control
#22Stacked memory chip device with enhanced data protection capability
#23Column repair in memory
#24Memory device including OTP memory cell and program method thereof
#25Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells per bit
#26Memory apparatus for in-chip error correction
#27Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application
#28Memory cell of static random access memory based on DICE structure
#29Integrated circuit and programmable device
#30Methods of storing and retrieving information for RRAM with multi-cell memory bits
#31Resistive random access memory having multi-cell memory bits
#32Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register
#33Reading of start-up information from different memory regions of a memory system
#34Apparatus and method capable of removing duplication write of data in memory
#35Raid data loss prevention
#36Memory scrubbing in a mirrored memory system to reduce system power consumption
#37Memory scrubbing in a mirrored memory system to reduce system power consumption
#38Storage device and data control method for storage error control
#39Single and double chip space
#40Method and apparatus for performing data recovery in a raid storage
#41Redundant array of independent NAND for a three-dimensional memory array
#42Raid data loss prevention
#43Redundancy memory device comprising a plurality of selecting circuits
#44Memory scrubbing in a mirrored memory system to reduce system power consumption
#45Memory scrubbing in a mirrored memory system to reduce system power consumption
#46Method, computer, and apparatus for migrating memory data
#47Multichip dual write
#48Impedance calibration circuit, and semiconductor memory and memory system using the same
#49Redundant magnetic tunnel junctions in magnetoresistive memory
#50Reliable readout of fuse data in an integrated circuit
#51Apparatuses and methods for memory management
#52Semiconductor storage device
#53Method, computer, and apparatus for migrating memory data
#54Electronic device and data-management method thereof
#55Secure memory which reduces degradation of data
#56Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory cells per bit
#57Logical unit operation
#58Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
#59Memory device, memory control device, and memory control method
#60Differential MRAM structure with relatively reversed magnetic tunnel junction elements enabling writing using same polarity current
#61MRAM with current-based self-referenced read operations
#62Secure memory which reduces degradation of data
#63Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
#64System and method of using stripes for recovering data in a flash storage system
#65DATA PROCESSING DEVICE AND METHOD OF READING TRIMMING DATA
#66NONVOLATILE SEMICONDUCTOR MEMORY AND STORAGE DEVICE
#67Extending Data Retention of a Data Storage Device Downhole
#68Method and apparatus for saving and restoring soft repair data
#69Method of storing E-fuse data in flash memory device
#70Memory system with redundant data storage and error correction
#71System for dynamically distributing an available memory resource to redundant and non-redundant storage areas using RAM routing logic
#72SYSTEM AND METHOD OF RECOVERING DATA IN A FLASH STORAGE SYSTEM
#73Failover control of dual controllers in a redundant data storage system
#74Backup method and disk array apparatus
#75Memory device, host circuit, circuit board, liquid receptacle, method of transmitting data stored in a nonvolatile data memory section to a host circuit, and system including a host circuit and a memory device detachably attachable to the host circuit
#76Embedded electronic device and method for storing data
#77CIRCUIT ARRANGEMENT AND METHOD FOR DATA PROCESSING
#78Nonvolatile memory device, system, and programming method
#79Microprocessor boot-up controller connected to a processor and NAND flash memory for controlling the boot-up of a computer device
#80Data mirroring in serial-connected memory system
#81Logical unit operation
#82Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
#83Data processing device and method of reading trimming data
#84SEMICONDUCTOR MEMORY DEVICE
#85MULTI-LEVEL CELL FLASH MEMORY
#86Memory device internal parameter reliability
#87Memory module
#88Microprocessor memory management
#89Nonvolatile memory with self recovery
#90Methods of operating multi-bit flash memory devices and related systems
#91Apparatus and method to prevent data loss in nonvolatile memory
#92Semiconductor device and controlling method for the same
#93METHOD OF STORING E-FUSE DATA IN FLASH MEMORY DEVICE
#94Flash memory device and method for providing initialization data
#95Methods and apparatus for employing redundant arrays to configure non-volatile memory
#96Repairing integrated circuit memory arrays
#97Mini flash disk with data security function
#98System for elevator electronic safety device
#99Data readout circuit of memory cells, memory circuit and method of reading out data from memory cells
#100MEMORY MULTI-BIT ERROR CORRECTION AND HOT REPLACE WITHOUT MIRRORING
#101Memory controller and method of controlling memory
#102Device and method having a memory array storing each bit in multiple memory cells
#103Microprocessor boot-up controller, nonvolatile memory controller, and information processing system
#104Microprocessor boot-up controller, nonvolatile memory controller, and information processing system
#105Early detection of storage device degradation
#106Nonvolatile semiconductor memory device and method of rewriting data thereof
#107Nonvolatile semiconductor memory device and method of rewriting data thereof
#108ROM redundancy in ROM embedded DRAM
#109Semiconductor memory device
#110Failover control of dual controllers in a redundant data storage system
#111Memory with fault tolerant reference circuitry
#112Device and method having a memory array storing each bit in multiple memory cells
#113Data reconstruction method and system wherein timing of data of data reconstruction is controlled in accordance with conditions when a failure occurs
#114Nonvolatile semiconductor memory device and method of rewriting data thereof
#115Thin film magnetic memory device for programming required information with an element similar to a memory cell information programming method
#116Microprocessor boot-up controller, nonvolatile memory controller, and information processing system
#117Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system
#118Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency
#119Device having a memory array storing each bit in multiple memory cells
#120Column repair in memory