199829 ⎘
Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
Sub-classes:Stacked 3D Memory Architecture for an Artificial Reality Device
#2Semiconductor device and semiconductor memory apparatus including the semiconductor device
#3Activation of memory core circuits in an integrated circuit
#4Activation of memory core circuits in an integrated circuit
#5Activation of memory core circuits in an integrated circuit
#6Sequential power transitioning of multiple data decoders
#7Memory system and method for operating the same
#8Mirroring in three-dimensional stacked memory
#9Memory device with improved refresh scheme for redundancy word line
#10Memory with redundancy
#11Addressing auto address assignment and auto-routing in NAND memory network
#12System and method for providing voltage supply protection in a memory device
#13Three dimensional(3D) memory device sparing
#14Blocking current leakage in a memory array
#15Apparatus and method for repairing an integrated circuit
#16Implementing column redundancy steering for memories with wordline repowering
#17Semiconductor memory device and method of operating the same
#18Methods for testing a memory embedded in an integrated circuit
#19Semiconductor memory apparatus
#20Semiconductor device having redundant bit line provided to replace defective bit line
#21Semiconductor memory device and method for testing the same
#22Low-power redundancy for non-volatile memory
#23Structure and method for decoding read data-bus with column-steering redundancy
#24Power source circuit and semiconductor memory circuit using the same
#25Repair circuit including repair controller
#26Integrated circuit having an embedded memory and method for testing the memory
#27SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
#28Semiconductor device, semiconductor package and memory repair method
#29OPERATION METHOD OF SUPPRESSING CURRENT LEAKAGE IN A MEMORY AND ACCESS METHOD FOR THE SAME
#30MEMORY DEVICE WITH REDUCED CURRENT LEAKAGE
#31Memory System having Spare Memory Devices Attached to a Local Interface Bus
#32Sense amplifier with redundancy
#33Methods and apparatus for disabling a memory-array portion
#34Semiconductor memory device and control method thereof
#35Current limit circuit and semiconductor memory device
#36Three-dimensional memory device
#37Disabling faulty flash memory dies
#38SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING REDUNDANCY THEREOF
#39Semiconductor device having coupling elimination circuit
#40Managing redundant memory in a voltage island
#41Block repair apparatus and method thereof
#42Semiconductor memory device and control method thereof
#43Integrated circuit memory device responsive to word line/bit line short-circuit
#44Circuit and method to find wordline-bitline shorts in a DRAM
#45Byte writeable memory with bit-column voltage selection and column redundancy
#46Semiconductor memory device with transfer switch and method of operating the device
#47Memory device having selectively decoupleable memory portions and method thereof
#48Semiconductor memory apparatus and method of controlling redundancy thereof
#49Dynamic random access memory (DRAM) for suppressing a short-circuit current
#50Dynamic memory refresh configurations and leakage control methods
#51Bitline exclusion in verification operation
#52Method of operating a memory system
#53Circuits and methods for repairing defects in memory devices
#54Circuits and methods for repairing defects in memory devices
#55Disabling faulty flash memory dies
#56Current reduction circuit of semiconductor device
#57Redundant wordline deactivation scheme
#58Current limit circuit and semiconductor memory device
#59Current reduction circuit of semiconductor device
#60Bitline exclusion in verification operation
#61Test mode for detecting a floating word line
#62Fabric light control window covering
#63Semiconductor memory device and a method of redressing a memory cell
#64Address comparator of semiconductor memory device
#65Memory circuit with redundant memory cell array allowing simplified shipment tests and reduced power consumptions
#66Zero-enabled fuse-set
#67Refresh-free dynamic semiconductor memory device
#68Memory device for reducing leakage current
#69Integrated semiconductor memory comprising at least one word line and comprising a multiplicity of memory cells
#70Electronic memory apparatus, and method for deactivating redundant bit lines or word lines
#71Dynamic semiconductor memory device
#72Bit line discharge control method and circuit for a semiconductor memory
#73Reduced power redundancy address decoder and comparison circuit
#74Device and method for breaking leakage current path of memory device and structure of memory device
#75Memory bit line leakage repair
#76Device and method for breaking leakage current path
#77Redundancy scheme for a memory integrated circuit
#78Reduced power consumption in integrated circuits with fuse controlled redundant circuits
#79Semiconductor memory device which selectively controls a local input/output line sense amplifier
#80Circuits and methods for repairing defects in memory devices
#81Reduced power redundancy address decoder and comparison circuit
#82Stacked 3D memory architecture for power optimization
#83Memory system controlling power supply and control circuit for controlling power supply