ClassID:

199841

G11C29/886 - CPC Classification

Classification description:

Checking stores for correct operation ; Subsequent repair ; Testing stores during standby or offline operation; Masking faults in memories by using spares or by reconfiguring with partially good memories combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device

Recent Application in this class:
#1
20250342900
2025-11-06

VIRTUAL BLOCK MULTI-PLAN ACCESS SYSTEM

#2
20250266119
2025-08-21

OPTIMIZED HANDLING OF NEIGHBOR PLANE DISTURB ISSUES

#3
20250232829
2025-07-17

Data Storage Device and Method for Read Disturb Mitigation During Low-Power Modes

#4
20250104799
2025-03-27

MIXED-MODE VIRTUAL BLOCK GENERATION

#5
20220392562
2022-12-08

AUTOMATICALLY SKIP BAD BLOCK IN CONTINUOUS READ OR SEQUENTIAL CACHE READ OPERATION

#6
20220277802
2022-09-01

Grown bad block management in a memory sub-system

#7
20210391029
2021-12-16

Grown bad block management in a memory sub-system

#8
20210375389
2021-12-02

Dual damascene crossbar array for disabling a defective resistive switching device in the array

#9
20210350871
2021-11-11

Uncorrectable ECC

#10
20210166777
2021-06-03

MEMORY REPAIR CIRCUIT, MEMORY REPAIR METHOD, AND MEMORY MODULE USING MEMORY REPAIR CIRCUIT

#11
20210012851
2021-01-14

Uncorrectable ECC

#12
20200310896
2020-10-01

Apparatus and method for checking an operation status of a memory device in a memory system

#13
20200211665
2020-07-02

Memory system and operating method thereof

#14
20190310774
2019-10-10

Memory system and operating method thereof

#15
20190138229
2019-05-09

Memory device and memory system including the same

#16
20190108892
2019-04-11

System and method for post-package repair across DRAM banks and bank groups

#17
20180374559
2018-12-27

Column repair in memory

#18
20180366210
2018-12-20

Memory system for accessing recovered super block and operating method thereof

#19
20180004594
2018-01-04

Mapping around defective flash memory of a storage array

#20
20170031787
2017-02-02

Performance optimization of read functions in a memory system

#21
20170031595
2017-02-02

Performance optimization of read functions in a memory system

#22
20160041869
2016-02-11

Masking defective bits in a storage array

#23
20150089327
2015-03-26

Semiconductor memory devices and memory systems including the same

#24
20140347943
2014-11-27

Semiconductor package including stacked chips and method of fabricating the same

#25
20140091834
2014-04-03

3D IC structure and method

#26
20140006848
2014-01-02

Bad block management mechanism

#27
20130339820
2013-12-19

Three dimensional (3D) memory device sparing

#28
20130120021
2013-05-16

3D IC structure and method

#29
20100325343
2010-12-23

Memory system

#30
20090142861
2009-06-04

Method of manufacturing flash memory device

#31
20090137070
2009-05-28

Manufacturing method for partially-good memory modules with defect table in EEPROM

#32
20070288805
2007-12-13

Method and apparatus for storing failing part locations in a module

#33
20070201293
2007-08-30

Testing method for permanent electrical removal of an integrated circuit output

#34
20060028864
2006-02-09

Enhanced functionality in a two-terminal memory array

#35
20050180234
2005-08-18

Testing method for permanent electrical removal of an intergrated circuit output after packaging

#36
20050027951
2005-02-03

Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency

#37
15600409
2018-09-04

Column repair in memory