199407 ⎘
Arrangements for writing information into, or reading information out from, a digital store; Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management Timing of memory operations based on dummy memory elements or replica circuits
SRAM WITH TRACKING CIRCUITRY FOR REDUCING ACTIVE POWER
#2Turbo Mode SRAM for High Performance
#3STORAGE DEVICE FOR GENERATING A DELAY SIGNAL, AND A METHOD OF OPERATING THE SAME
#4OFFSET CANCELLATION
#5ADJUSTABLE DELAY PROPAGATION OF A CONTROL SIGNAL TO DIFFERENT PAGE BUFFER DRIVER GROUPS
#6MEMORY DEVICE INCLUDING VOLTAGE AND TEMPERATURE SENSING CIRCUIT AND METHOD FOR MANAGING OPERATION THEREOF
#7FAST AND EFFICIENT VERIFY RECOVERY AND ARRAY DISCHARGE FOR 3D NAND MEMORY ARRAYS
#8Systems and methods for controlling common mode level for sense amplifier circuitry
#9Methods of operating a near memory processing-dual in-line memory module (NMP-DIMM) for performing a read operation and an adaptive latency module and a system thereof
#10SRAM with tracking circuitry for reducing active power
#11Mixing normal and reverse order programming in NAND memory devices
#12EFFICIENT IMAGE DATA DELIVERY FOR AN ARRAY OF PIXEL MEMORY CELLS
#13SRAM with tracking circuitry for reducing active power
#14MEMORY SYSTEM PERFORMING PERFORMANCE ADJUSTING OPERATION
#15Memory device with adjustable delay propagation of a control signal to different page buffer driver groups
#16Memory array reset read operation
#17Turbo mode SRAM for high performance
#18Offset cancellation
#19Control method and controller of program suspending and resuming for memory
#20TSV check circuit with replica path
#21Control method and controller of program suspending and resuming for memory
#22Delay locked loop circuit and semiconductor memory device having the same
#23Memory macro and method of operating the same
#24Memory circuit including tracking circuit
#25TSV check circuit with replica path
#26Semiconductor apparatus and method for controlling semiconductor apparatus
#27Memory interface circuit, memory storage device and signal generation method
#28Memory array reset read operation
#29Semiconductor storage device
#30Memory components and controllers that calibrate multiphase synchronous timing references
#31Semiconductor device
#32Memory macro and method of operating the same
#33Memory circuit including tracking circuit
#34Offset cancellation
#35Integrated circuit
#36Semiconductor device providing an output in response to a read command or a mode-register read command
#37Memory device, driving method thereof, semiconductor device, electronic component, and electronic device
#38Circuitry for tracking bias voltage behavior
#39Semiconductor device
#40Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
#41Memory macro and method of operating the same
#42Memory devices and memory systems including the same
#43Controller and operating method thereof
#44Address control circuit and semiconductor device including the same
#45Dummy bitline circuitry
#46Reading from a mode register having different read and write timing
#47Turbo mode SRAM for high performance
#48Memory circuit having tracking circuit including series-connected transistors
#49Multiple data rate memory
#50Memory array reset read operation
#51Dummy bitline circuitry
#52Nonvolatile memory device and operating method of nonvolatile memory device
#53Controller and operating method thereof
#54Static random access memory (SRAM) array power supply circuit
#55Integrated circuit
#56Address control circuit and semiconductor device including the same
#57Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
#58Static random access memory cell capable of performing differential operation
#59Memory macro and method of operating the same
#60Semiconductor device
#61Memory, information processing system, and method of controlling memory
#62Method of operating tracking circuit
#63Semiconductor device and semiconductor system
#64Non-volatile memory device having dummy cells and memory system including the same
#65Self-latch sense timing in a one-time-programmable memory architecture
#66Memory components and controllers that calibrate multiphase synchronous timing references
#67Operating method of a magnetic memory device
#68Integrated circuit using shaping and timing circuitries
#69Memory device, driving method thereof, semiconductor device, electronic component, and electronic device
#70Memory device with progressive row reading and related reading method
#71Control device for controlling semiconductor memory device
#72Semiconductor device
#73Memory device having command window generator
#74Sense amplifier enabling scheme
#75Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power
#76Automatic delay-line calibration using a replica array
#77Memory device having latency control circuit for controlling data write and read latency
#78Semiconductor device
#79Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of memory controller
#80Memory components and controllers that calibrate multiphase synchronous timing references
#81Circuits for control of time for read operation, using a current mirror circuit to mirror a reference current into the dummy device and generates time control signals based on the mirrored current
#82Memory circuit having tracking circuit including series-connected transistors
#83Semiconductor storage device
#84Method and control circuit for memory macro
#85Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
#86Memory timing circuit
#87Apparatus for reducing write minimum supply voltage for memory
#88Tracking cell and method
#89Semiconductor device
#90Memory tracking scheme
#91Semiconductor memory device using delays to control column signals for different memory regions
#92Two phase write scheme to improve low voltage write ability in dedicated read and write port SRAM memories
#93Self-timer for sense amplifier in memory device
#94Concurrent read and write operations in a serial flash device
#95Semiconductor device and operating method thereof
#96Tracking signals in memory write or read operation
#97Tracking bit cell and method
#98Three-dimensional memory device and operating method of a storage device including the same
#99Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of memory controller
#100Memory array and method of operating the same
#101Serial memory device alert of an external host to completion of an internally self-timed operation
#102Electronic device
#103Tracking mechanisms
#104NOR-OR Decoder
#105Multi-cycle write leveling
#106Apparatus for time domain offset cancellation to improve sensing margin resistive memories
#107Area-efficient process-and-temperature-adaptive self-time scheme for performance and power improvement
#108Tracking mechanism for writing to a memory cell
#109Tracking bit cell
#110Circuit to generate a sense amplifier enable signal
#111Read tracking mechanism
#112Semiconductor device
#113Memory timing circuit
#114Programmable delay introducing circuit in self timed memory
#115Signal control circuit, information processing apparatus, and duty ratio calculation method
#116Selective dual cycle write operation for a self-timed memory
#117Mobile device and a method of controlling the mobile device
#118Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information
#119SRAM restore tracking circuit and method
#120Semiconductor device
#121Far end resistance tracking design with near end pre-charge control for faster recovery time
#122Semiconductor memory devices and semiconductor systems including the same
#123Memory interface offset signaling
#124Dual asynchronous and synchronous memory system
#125Tracking circuit
#126Multiple bitcells tracking scheme semiconductor memory array
#127Tracking circuit
#128Write-tracking circuitry for memory devices
#129Nonvolatile memory and method with improved I/O interface
#130Bit cell internal voltage control
#131Memory device with control circuitry for generating a reset signal in read and write modes of operation
#132Memory system incorporating a circuit to generate a delay signal and an associated method of operating a memory system
#133Circuits and methods of a self-timed high speed SRAM
#134Multiple bitcells tracking scheme semiconductor memory array
#135Using a reference bit line in a memory
#136Channel hot carrier tolerant tracking circuit for signal development on a memory SRAM
#137Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delay
#138Initializing dummy bits of an SRAM tracking circuit
#139Semiconductor memory device with sequentially generated delay signals
#140Memory device with bi-directional tracking of timing constraints
#141Tracking signals in memory write or read operation
#142Memory device
#143Tracking mechanism for writing to a memory cell
#144Memory device with separately controlled sense amplifiers
#145Read-current and word line delay path tracking for sense amplifier enable timing
#146Semiconductor memory apparatus
#147Apparatus for reducing write minimum supply voltage for memory
#148Memory components and controllers that calibrate multiphase synchronous timing references
#149Far end resistance tracking design with near end pre-charge control for faster recovery time
#150Memory having self-timed edge-detection write tracking
#151Memory device having control circuitry for write tracking using feedback-based controller
#152NOR-OR decoder
#153Write self timing circuitry for self-timed memory
#154Memory device having control circuitry configured for clock-based write self-time tracking
#155SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED BIT LINES AND SYSTEM INCLUDING THE SAME
#156MEMORY DEVICE HAVING CONTROL CIRCUITRY FOR SENSE AMPLIFIER REACTION TIME TRACKING
#157Handling of write operations within a memory device
#158Semiconductor memory device
#159Control signal generator for use with a command decoder
#160Voltage mode sensing for low power flash memory
#161Tracking mechanisms
#162Tracking for write operations of memory devices
#163Mimicking multi-voltage domain wordline decoding logic for a memory array
#164System and method for modifying activation of a sense amplifier
#165Memory architecture and design methodology with adaptive read
#166Semiconductor memory device
#167Circuit and method for generating a sense amplifier enable signal based on a voltage level of a tracking bitline
#168Tracking cell and method for semiconductor memories
#169Semiconductor memory read and write access
#170SRAM memory device and testing method thereof
#171Tracking bit cell
#172Memory apparatus
#173Semiconductor memory device and data reading method
#174Semiconductor device having hierarchically structured bit lines and system including the same
#175Semiconductor memory device
#176Nor-or decoder
#177Semiconductor device
#178Tracking scheme for memory
#179SEMICONDUCTOR STORAGE DEVICE
#180SRAM timing cell apparatus and methods
#181Programmable delay introducing circuit in self-timed memory
#182Memory device with robust write assist
#183Memory circuit and a tracking circuit thereof
#184Semiconductor memory device
#185Semiconductor memory device with delay circuit and sense amplifier circuit
#186Semiconductor storage device
#187Non-volatile memory with improved sensing by reducing source line current
#188Memory
#189Memory device with phase distribution circuit for controlling relative durations of precharge and active phases
#190Efficient word lines, bit line and precharge tracking in self-timed memory device
#191Semiconductor memory
#192Programmable tracking circuit for tracking semiconductor memory read current
#193NOR-OR DECODER
#194MEMORY DEVICE AND SENSE CIRCUITRY THEREFOR
#195System and method of operating a memory device
#196Semiconductor memory device
#197SRAM delay circuit that tracks bitcell characteristics
#198Latency circuit and semiconductor device comprising same
#199Non-volatile memory with improved sensing by reducing source line current
#200Semiconductor device having hierarchically structured bit lines and system including the same
#201Semiconductor memory device and method of controlling same
#202Semiconductor integrated circuit
#203SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING WORD LINE POTENTIAL
#204Semiconductor memory device
#205Self-timing for a multi-ported memory system
#206Semiconductor memory device
#207Semiconductor integrated circuit device and operating method thereof
#208Semiconductor memory device
#209Semiconductor integrated circuit
#210Semiconductor memory device
#211Resistance variable memory device and system
#212Reset circuit for termination of tracking circuits in self timed compiler memories
#213Semiconductor memory including voltage detection circuit for generating sense amplifier signal
#214Efficient word lines, bit line and precharge tracking in self-timed memory device
#215Non-volatile memory with improved sensing by reducing source line current
#216Dual mode accessing signal control apparatus and dual mode timing signal generating apparatus
#217Synchronous memory device
#218Semiconductor memory device having replica circuit
#219SENSE AMPLIFIER READ LINE SHARING
#220Phase change memory device with dummy cell array
#221Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer
#222Semiconductor storage device
#223Decoder with memory
#224LOW-POWER SENSE AMPLIFIER
#225RAM WITH INDEPENDENT LOCAL CLOCK
#226Efficient sense command generation
#227Semiconductor integrated circuit
#228Semiconductor memory device
#229Memory device with delay tracking for improved timing margin
#230Clock and control signal generation for high performance memory devices
#231Semiconductor memory device
#232Semiconductor memory device
#233Memory having a dummy bitline for timing control
#234Pulse width control for read and write assist for SRAM circuits
#235Semiconductor memory device including a static memory cell
#236System and method for compensating for PVT variation effects on the delay line of a clock signal
#237Self-timing read architecture for semiconductor memory and method for providing the same
#238Semiconductor memory device having replica circuit
#239Method for compensated sensing in non-volatile memory
#240Semiconductor memory device having replica circuit
#241Semiconductor integrated circuit
#242CLOCK CONTROL METHOD AND APPARATUS FOR A MEMORY ARRAY
#243Semiconductor memory device
#244Method and apparatus for a dummy SRAM cell
#245Semiconductor memory device
#246Programmable delay introducing circuit in self timed memory
#247Self timing write architecture for semiconductor memory and method for providing the same
#248Semiconductor integrated circuit having a switch circuit that outputs reference clock until PLL locks
#249Sensing margin varying circuit and method thereof
#250Synchronous memory device
#251Semiconductor memory having dummy bit line precharge/discharge circuit
#252Tracking circuit for a memory device
#253Semiconductor integrated circuit
#254Semiconductor memory including self-timing circuit
#255Clock control method and apparatus for a memory array
#256Reference sense amplifier for non-volatile memory
#257Method for compensated sensing in non-volatile memory
#258Semiconductor integrated circuit with a cache circuit configured to determine an optimal portion to stop the operation between a sense amplifier and an output circuit based on the system clock
#259DQS for data from a memory array
#260Static random access memory (SRAM) with replica cells and a dummy cell
#261Semiconductor memory device and circuit layout of dummy cell
#262Semiconductor memory device having ECC circuit
#263Semiconductor memory device and timing control method
#264Semiconductor integrated circuit
#265Tracking circuit enabling quick/accurate retrieval of data stored in a memory array
#266Sense amplifier for a memory array
#267Semiconductor device having sense amplifier driver that controls enabling timing
#268Semiconductor device having automatic controlled delay circuit and method therefor
#269Semiconductor integrated circuit device
#270Semiconductor memory device
#271Device for receiving single-ended signal of light emitting diode control card and forwarding as differential signals
#272Read tracking scheme for a memory device
#273Multi-bit pulsed latch including serial scan chain
#274Control methods and memory systems using the same
#275Semiconductor memory device outputting status signal and operating method thereof
#276Memory device
#277Memory device and driving circuit adopted by the memory device