Transfer of non-associated information on flash memory devices

Memory module having buffer and memory ranks addressable by respective selection signal

Semiconductor package for forming a double die package (DDP)

Semiconductor memory device for independently selecting mode of memory bank and method of controlling thereof

Semiconductor memory device

Memory and operation method thereof

Semiconductor Memory System Having Plurality of Ranks Incorporated Therein

Processor system using synchronous dynamic memory

Semiconductor memory apparatus

Write driving circuit and semiconductor memory apparatus using the same

SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR DEVICE, MEMORY SYSTEM AND REFRESH CONTROL METHOD

Decoding control with address transition detection in page erase function

Power savings for memory with error correction mode

Semiconductor memory integrated circuit

Integrated circuit, method of reading data stored within a memory device of an integrated circuit, method of writing data into a memory device of an integrated circuit, memory module, and computer program

Memory device, memory controller and memory system

Circuit for use in a multiple block memory

Semiconductor memory device and refresh control method

Memory device, memory controller and memory system

Synchronous memory circuit

Memory device and method having programmable address configurations

Semiconductor memory device including a static memory cell

Multi-path accessible semiconductor memory device having mailbox areas and mailbox access control method thereof

Data processing system and image processing system

Accessing memory using multi-tiling

WEAR LEVELING TECHNIQUES FOR FLASH EEPROM SYSTEMS

SEMICONDUCTOR MEMORY DEVICE HAVING INTERNAL VOLTAGE GENERATION CIRCUITS

Flash EEPROM System

Memory device, memory controller and memory system

Memory device, memory controller and memory system

Memory device, memory controller and memory system

Method and system for providing a magnetic memory structure utilizing spin transfer

Method for operating a data storage apparatus employing passive matrix addressing

Semiconductor memory, operating method of semiconductor memory, memory controller, and system

Semiconductor memory device with a plurality of bank groups each having a plurality of banks sharing a global line group

Static random access memory architecture

Low power memory device

Apparatus and method for producing device identifiers for serially interconnected devices of mixed type

Address assignment and type recognition of serially interconnected memory devices of mixed type

Voltage generating circuit and semiconductor memory device with the same

Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods

Semiconductor memory device including a column decoder array

Semiconductor memory device including a write recovery time control circuit

MEMORY ARRAY WITH BIT LINES COUNTERING LEAKAGE

Semiconductor device

Memory bus output driver of a multi-bank memory device and method therefor

Memory module and memory device

Semiconductor memory device and data error detection and correction method of the same

Method and apparatus for communicating command and address signals

Non-volatile memory with improved program-verify operations

Integrated circuit memory device having delayed write timing based on read response time

Semiconductor memory apparatus and method of controlling redundancy thereof

Memory accessing circuit system

Dynamic word line drivers and decoders for memory arrays

Semiconductor memory device

Semiconductor storage device

End of Life Recovery and Resizing of Memory Cards

Memory device and method of reading/writing data from/into a memory device

Semiconductor memory and system

Memory module decoder

Semiconductor device having a plurality of memory chips

Multi-column addressing mode memory system including an integrated circuit memory device

Methods and apparatus to provide refresh for local out of range read requests to a memory device

MEMORY WITH MEMORY BANKS AND MODE REGISTERS AND METHOD OF OPERATING A MEMORY

Semiconductor memory device and refresh control method thereof

Nonvolatile memory

Block status storage unit of flash memory device

Memory device and method having multiple address, data and command buses

Semiconductor memory device realizing high-speed access

Method of Controlling A Memory Device Having a Memory Core

Semiconductor memory for disconnecting a bit line from a sense amplifier in a standby period and memory system including the semiconductor memory

Method and computer for reducing power consumption of a memory

Daisy chainable memory chip

Daisy chainable memory chip

Block erase for volatile memory

System and method for simulating an aspect of a memory circuit

SYSTEM AND METHOD FOR STORING AT LEAST A PORTION OF INFORMATION RECEIVED IN ASSOCIATION WITH A FIRST OPERATION FOR USE IN PERFORMING A SECOND OPERATION

Method for using two data busses for memory array block selection

Method for using dual data-dependent busses for coupling read/write circuits to a memory array

Dual data-dependent busses for coupling read/write circuits to a memory array

Semiconductor memory device

System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits

Flash memory device and multi-block erase method

Memory array incorporating two data busses for memory array block selection

High bandwidth one time field-programmable memory

System and method for monitoring trading

Device and method having a memory array storing each bit in multiple memory cells

Multi-bank memory

Memory systems and memory modules

Semiconductor memory device

Memory chip architecture having non-rectangular memory banks and method for arranging memory banks

Row address controller

Semiconductor memory apparatus having plurality of sense amplifier arrays having different activation timing

Semiconductor memory device having stacked bank structure

Serial memory comprising means for protecting an extended memory array during a write operation

Random access memory including multiple state machines

Synchronous global controller for enhanced pipelining

Automatically generating an input sequence for a circuit design using mutant-based verification

Semiconductor integrated circuit having data input/output circuit and method for inputting data using the same

Clock circuit for semiconductor memory

Hybrid memory device with single interface

Method for writing to multiple banks of a memory device

In-circuit Vt distribution bit counter for non-volatile memory devices

Memory device and method having banks of different sizes

Method and system for providing a magnetic memory structure utilizing spin transfer

Methods of programming memory cells using manipulation of oxygen vacancies

Semiconductor memory device

Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling

One-transistor composite-gate memory

Memory module and methods for making and using the same

High-speed controller for phase-change memory peripheral device

Semiconductor memory device

Memory control method and apparatuses

Dual chip package

Attribute cache memory

Semiconductor integrated circuits with power reduction mechanism

Dual-plane type flash memory device having random program function and program operation method thereof

User selectable banks for DRAM

Integrated circuit memory device having delayed write timing based on read response time

Row selector for a semiconductor memory device

Semiconductor storage device

Reducing leakage current in memory device using bitline isolation

Memory device with read data from different banks

Semiconductor memory, memory system, and operation method of memory system

Segmented column virtual ground scheme in a static random access memory (SRAM) circuit

Non-volatile phase-change memory device and associated program-suspend-read operation

Integrated circuit having a word line driver

Phase-change random access memory device

Memory system having delayed write timing

Multi-port semiconductor memory device and signal input/output method therefor

Reduced pin count synchronous dynamic random access memory interface

Semiconductor chip and semiconductor chip package comprising semiconductor chip

Fast random access DRAM management method including a method of comparing the address and suspending and storing requests

Semiconductor device with improved power supply arrangement

Semiconductor device with improved power supply arrangement

Multi-port semiconductor memory device and method for accessing and refreshing the same

Non-volatile memory with improved program-verify operations

Methods to make DRAM fully compatible with SRAM

Integrated circuit memory device with delayed write command processing

Command generating circuit and semiconductor memory device having the same

On-chip data grouping and alignment

Phase change memory device

Memory device row and/or column access efficiency

Nonvolatile semiconductor memory device

Address converter semiconductor device and semiconductor memory device having the same

Phase-change memory device

Semiconductor memory device and method for operating a semiconductor memory device

Row decoder for preventing leakage current and semiconductor memory device including the same

Multi-port semiconductor memory device having variable access paths and method

Semiconductor memory device

Integrated circuit memory device having delayed write capability

Memory control circuit in a memory chip

Apparatus and method for pipelined memory operations

Apparatus and method of controlling bank of semiconductor memory

Block management for mass storage

Data write-in method for flash memory

Latency control circuit and method thereof and an auto-precharge control circuit and method thereof

Semiconductor memory device with hierarchical bit line structure

Semiconductor storage device

Method for operating a data storage apparatus employing passive matrix addressing

Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground

High density three dimensional semiconductor die package

High performance tiling for RRAM memory

Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration

Directed auto-refresh for a dynamic random access memory

Directed auto-refresh for a dynamic random access memory

Memory having directed auto-refresh

Low power memory control circuits and methods

Semiconductor memory device and transmission/reception system provided with the same

Apparatus for storing memory words

CPU address decoding with multiple target resources

Multi-port memory device

Multi-port memory device with serial input/output interface

Semiconductor memory device sharing sense amplifier

Processor system using synchronous dynamic memory

Semiconductor integrated circuits with power reduction mechanism

Integrated memory core and memory interface circuit

Semiconductor memory system and semiconductor memory chip

Storage device and control method of storage device

Memory system for selectively transmitting command and address signals

Low power memory device

Memory device and method having separate write data and read data buses

Memory device and method having multiple address, data and command buses

Data processor memory circuit

Method of controlling refresh operation in multi-port DRAM and a memory system using the method

Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies

Banked cache with multiplexer

Memory module and memory system having the same

Micro-tile memory interfaces

Flexible capacity memory IC

Addressing, command protocol, and electrical interface for non-volatile memories utilized in recording usage counts

Integrated semiconductor memory

Partial page scheme for memory technologies

Memory interface

Memory-module board layout for use with memory chips of different data widths

Method for setting a second rank address from a first rank address in a memory module

Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method

Reducing power consumption in integrated circuits

Non-volatile semiconductor memory device and semiconductor disk device

Memory module and memory system

Memory module with a circuit providing load isolation and memory domain translation

Device and method for performing a partial array refresh operation

Semiconductor device that enables simultaneous read and write/read operation

One-transistor composite-gate memory

Data processor memory circuit

Memory arrangement having a plurality of RAM chips

Semiconductor device with power down arrangement for reduce power consumption

Memory architecture

Semiconductor memory device

Using redundant memory for extra features

Using redundant memory for extra features

Semiconductor storage device having a plurality of stacked memory chips

Column path circuit

Common wordline flash array architecture

Memory device and method having programmable address configurations

Semiconductor integrated circuit device

Multiple memory device management

Memory stacking system and method

Multi-bank memory

Non-volatile memory device with erase address register

Nonvolatile ferroelectric memory and control device using the same

Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device

Semiconductor memory devices and methods of operating the same

Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays

Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method

Semiconductor memory apparatus

Multiple flash memory device management

Multi-port memory device providing protection signal

On-chip data grouping and alignment

Semiconductor integrated circuits with power reduction mechanism

Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)

Memory device, memory controller and method for operating the same

Method of configuring memory cell array block, method of addressing the same, semiconductor memory device and memory cell array block

Thin-film magnetic memory device with memory cells having magnetic tunnel junction

Multi-rank memory module that emulates a memory module having a different number of ranks

Controlling an addressable array of circuits

Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation

Semiconductor memory device

High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode

Memory bank structure

Semiconductor integrated circuit device

Method and system for providing sensing circuitry in a multi-bank memory device

Semiconductor memory device and package thereof, and memory card using the same

Multi-column addressing mode memory system including an integrated circuit memory device

System and method for storing data

Integrated circuit memory device supporting an N bit prefetch scheme and a 2N burst length

Semiconductor memory device with a stacked-bank architecture and method for driving word lines of the same

Semiconductor memory device having a plurality of latch circuits coupled to each read amplifier

Memory module decoder

Apparatus and method for pipelined memory operations

Serial memory comprising means for protecting an extended memory array during a write operation

Method and apparatus for a continuous read command in an extended memory array

Address coding method and address decoder for reducing sensing noise during refresh operation of memory device

One-transistor composite-gate memory

Memory stacking system and method

Memory device having staggered memory operations

Controller device and method for operating same

Device and method having a memory array storing each bit in multiple memory cells

Semiconductor memory device for simultaneously testing blocks of cells

Using redundant memory for extra features

Memory device and method having programmable address configurations

Floating-gate non-volatile memory architecture for improved negative bias distribution

System and method for updating data sectors in a non-volatile memory using logical block addressing

Flash memory device capable of reducing test time and test method thereof

Memory architecture

Flash EEprom system

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure

Method and apparatus for reading and writing to solid-state memory

Synchronous global controller for enhanced pipelining

Semiconductor memory device and semiconductor device

Device writing to a plurality of rows in a memory matrix simultaneously

Thin film magnetic memory device including memory cells having a magnetic tunnel junction

Semiconductor memory device having memory architecture supporting hyper-threading operation in host system

Semiconductor device having a power down mode

System for a memory device having a power down mode and method

Semiconductor memory device with a page mode

Semiconductor memory device and method of driving the same

Semiconductor device having a power down mode

Memory chip architecture having non-rectangular memory banks and method for arranging memory banks

Destructive-read random access memory system buffered with destructive-read memory cache

Method of accessing matrix data with address translation circuit that enables quick serial access in row or column directions

NOR flash memory device and method of shortening a program time

Nonaligned access to random access memory

Memory device and method having banks of different sizes

Memory device and method having banks of different sizes

System and module including a memory device having a power down mode

Method of reading multi-level NAND flash memory cell and circuit for the same

Memory device and method having banks of different sizes

Semiconductor device that enables simultaneous read and write/read operation

Bank selectable parallel test circuit and parallel test method thereof

Method and apparatus for initializing dynamic random access memory (DRAM) devices

Memory device

Method and apparatus for saving current in a memory device

Data storage unit, data storage controlling apparatus and method, and data storage controlling program

Method for making high performance semiconductor memory devices

Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program

Stacked layered type semiconductor memory device

Nonvolatile semiconductor memory device with a plurality of sectors