221483 ⎘
Manipulating of pulses not covered by one of the other main groups of this subclass; Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse; Fixed delay Avoiding variations of delay using feedback, e.g. controlled by a PLL
Sub-classes:CLOCK RECEIVER CIRCUIT WITH RAPID CLOCK SIGNAL SETTLING
#2Output control circuit for semiconductor apparatus and output driving circuit including the same
#3Non-overlapping clock generation
#4High resolution clock signal generator
#5Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line
#6Techniques for non-overlapping clock generation
#7Clock timing calibration circuit and clock timing calibration method for calibrating phase difference between different clock signals and related analog-to-digital conversion system using the same
#8Clock signal generation apparatus
#9Delay lock loop circuit, timing generator, semiconductor test device, semiconductor integrated circuit, and delay amount calibration method
#10Apparatus And Method For Test, Characterization, And Calibration Of Microprocessor-Based And Digital Signal Processor-Based Integrated Circuit Digital Delay Lines
#11Time constant calibration device and related method thereof
#12Oscillator with a stable oscillating frequency
#13Systems and methods for providing delayed signals
#14Method and apparatus for data transfer using a time division multiple frequency scheme supplemented with polarity modulation
#15Clock pulse generator apparatus with reduced jitter clock phase
#16AC technique for eliminating phase ambiguity in clocking signals
#17Data transfer using frequency notching of radio-frequency signals
#18System and method for calibrating the clock frequency of a clock generator unit over a data line
#19Apparatus and method for test, characterization, and calibration of microprocessor-based and digital signal processor-based integrated circuit digital delay lines
#20Substantially temperature independent delay chain
#21Self correcting scheme to match pull up and pull down devices
#22System and method for producing precision timing signals by controlling register banks to provide a phase difference between two signal paths
#23Automatic tuning of signal timing
#24Method and apparatus for data transfer using wideband bursts
#25Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process
#26Delay locked loop “ACTIVE Command” reactor