Managing signal transfers in semiconductor devices

Techniques to reduce the effect of pad asymmetry and signal routing on resolution of PWM or PFM signals

Glitch free input transition detector

Communication circuit apparatus and transceiver having the same

NMOS buffer for high-speed low-resolution current steering digital-to-analog converters

Processing clock signals

VOLTAGE OUTPUT CIRCUT

Level shifter with balanced duty cycle

INTERNAL SUPPLY VOLTAGE CIRCUIT OF AN INTEGRATED CIRCUIT

Delay-locked loop having a delay independent of input signal duty cycle variation

Input buffer

Time delay compensation and pulse width correction

Semiconductor integrated circuit having insulated gate field effect transistors

Pulse width adjusting circuit

Delay circuit including first and second internal delay circuits and a selection switch

LEVEL SHIFTER

Transmission circuit

Edge-timing adjustment circuit

Ratio asymmetric inverters, and apparatus including one or more ratio asymmetric inverters

Delay circuit having reduced duty cycle distortion

VOLTAGE CONTROLLED OSCILLATOR AND PHASE LOCKED LOOP CIRCUIT INCORPORATING THE SAME

Differential line compensation apparatus, method and system

Digital delay circuit

Clock Input/Output Device

Low power and duty cycle error free matched current phase locked loop

Differential line compensation apparatus, method and system

Semiconductor device and method for decreasing noise of output driver

Duty detector and duty detection/correction circuit including the same and method thereof

Buffer having predriver to help improve symmetry of rise and fall transitions in an output signal

Closed-loop independent DLL-controlled rise/fall time control circuit

Buffer circuit, buffer tree, and semiconductor device

Tunable delay circuit

Low frequency variation calibration circuitry