LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

REFERENCE CLOCK GENERATING CIRCUIT

FRAME DELAY TIME COUNTING CIRCUIT AND NEAR FIELD COMMUNICATION CARD INCLUDING THE SAME

SIGNAL TRANSMITTER, ELECTRONIC DEVICE, VEHICLE, AND INSULATED GATE DRIVER INTEGRATED CIRCUIT

REAL-TIME CLOCK GENERATION DEVICE AND REAL-TIME CLOCK GENERATION METHOD

METHODS AND APPARATUS TO PREVENT LOCK-UP OF HIGH-SPEED PSEUDO-DIFFERENTIAL FREQUENCY DIVIDER CIRCUITS

Pleat Counter

CAPACITIVE BATCH COUNTING TO SUPPORT ONE-WAY TIME-OF-FLIGHT OR OTHER OPERATIONS

SYNCHRONIZATION SIGNAL GENERATION CIRCUIT AND SYNCHRONIZATION METHOD BETWEEN MULTIPLE DEVICES

Frequency generator

PULSE SKIPPING CIRCUIT FOR WIRELESS SENSORS

CLOCK SIGNAL FREQUENCY DIVIDER, PROCESSING SYSTEM, PROCESSING DEVICE, AND CLOCK SIGNAL FREQUENCY DIVIDING METHOD

Electronic device, operating method thereof, and electronic system

Hierarchical statisically multiplexed counters and a method thereof

Computing apparatus triggered by an edge of a supply-line signal with a pulse width counter

LOOKAHEAD PRIORITY COLLECTION TO SUPPORT PRIORITY ELEVATION

MALICIOUS ATTACK PROTECTION CIRCUIT, SYSTEM-ON-CHIP INCLUDING THE SAME, AND OPERATING METHOD THEREOF

Sensor interface circuit and sensor module

Clock signal generation circuit

Radar system and related method of scanning remote objects

Pleat counter

Hierarchical statistically multiplexed counters and a method thereof

Low power frequency synthesizing apparatus

Cycle borrowing counter

Hierarchical statistically multiplexed counters and a method thereof

Lookahead priority collection to support priority elevation

Event counter circuits using partitioned moving average determinations and related methods

Broad range voltage-controlled oscillator

System and method for tracking machine use

Device and method for generating an output signal, formed as a pulse sequence, depending on a sensor signal

Pleat counter

Signal transfer device

Single-photon avalanche diode image sensor with photon counting and time-of-flight detection capabilities

Lookahead priority collection to support priority elevation

Hierarchical statistically multiplexed counters and a method thereof

Single-photon avalanche diode image sensor with photon counting and time-of-flight detection capabilities

Low-power local oscillator generation

Programmable clock divider

Semiconductor device

Counter and counting method

High-speed programmable clock divider

Hierarchical statisically multiplexed counters and a method thereof

Asynchronous high-speed programmable divider

Multi-modulus divider with power-of-2 boundary condition support

Multi-modulus prescaler with improved noise performance

Frequency synthesizer with dynamic phase and pulse-width control

Programmable synchronous clock divider

Semiconductor device

Low power digital self-gated binary counter

Apparatuses and methods for capturing data using a divided clock

Frequency divider and phase-locked loop including the same

Frequency division clock alignment using pattern selection

Frequency division clock alignment

Multi-modulus frequency divider and electronic apparatus including the same

Frequency divider and related electronic device

Programmable address-based write-through cache control

System and method for circuit card insertion tracking

LOW POWER DIVIDE-BY-SEVEN DIVIDER

Hierarchical statistically multiplexed counters and a method thereof

Counter

D-TYPE FLIP-FLOP AND CLOCK GENERATING CIRCUIT

Frequency divider apparatus

Clock frequency modulation method and clock frequency modulation apparatus

Performance and power improvement on DMA writes to level two combined cache/SRAM that is cached in level one data cache and line is valid and dirty

Switching power converter, clock module, control circuit and associated control method

Digital duty cycle correction

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Digital sample clock generator, a vibration gyroscope circuitry comprising such digital sample clock generator, an associated apparatus, an associated semiconductor device and associated methods

Counter circuit and semiconductor device including the same

High Speed Latch

Frequency scaling counter

Divided clock generation device and divided clock generation method

Clock generation circuit, processor system using same, and clock frequency control method

Fractional frequency divider with phase permutation

Non-volatile memory counter

Down converter and control method of the same

Phase-locked loop and integrated circuit chip including the same, and test system including the integrated circuit chip

Programmable delay unit

High speed RF divider

Semiconductor apparatus for controlling a frequency change of an internal clock

Continuous time counter

Timing monitor for PLL

Integer and half clock step division digital variable clock divider

Processing apparatus and valve operation checking method

RAM based implementation for scalable, reliable high speed event counters

Semiconductor device that can adjust propagation time of internal clock signal

Methods of controlling clocks in system on chip including function blocks, systems on chips and semiconductor systems including the same

Time detection circuit, ad converter, and solid state image pickup device

Circuit configuration and method for distributing pulses within a time interval

Non-volatile memory counter

Integer and half clock step division digital variable clock divider

Managing bandwidth allocation in a processing node using distributed arbitration

Lookahead Priority Collection to Support Priority Elevation

Enhanced pipelining and multi-buffer architecture for level two cache controller to minimize hazard stalls and optimize performance

Clock generation circuit, processor system using same, and clock frequency control method

Frequency synthesizer prescaler scrambling

Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines

Priority based exception mechanism for multi-level cache controller

Programmable mapping of external requestors to privilege classes for access protection

Cache pre-allocation of ways for pipelined allocate requests

Memory attribute sharing between differing cache levels of multilevel cache

Mechanism to Update the Status of In-Flight Cache Coherence In a Multi-Level Cache Hierarchy

Programmable address-based write-through cache control

Level one data cache line lock and enhanced snoop protocol during cache victims and writebacks to maintain level one data cache and level two cache coherence

Hazard prevention for data conflicts between level one data cache line allocates and snoop writes

Non-blocking, pipelined write allocates with allocate data merging in a multi-level cache system

Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU

Floating point multiplier circuit with optimized rounding calculation

Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme

Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers

Efficient level two memory banking to improve performance for multiple source traffic and enable deeper pipelining of accesses by reducing bank stalls

Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty

Distributed user controlled multilevel block and global cache coherence with accurate completion status

High speed RF divider

Dual register data path architecture with registers in a data file divided into groups and sub-groups

Cache with multiple access pipelines

Transaction info bypass for nodes coupled to an interconnect fabric

Interleaved Memory Access from Multiple Requesters

Requester based transaction status reporting in a system with multi-level memory

Closed loop adaptive voltage scaling

Programmable digital clock signal frequency divider module and modular divider circuit

Data processing method and solid-state image pickup device

NOVEL METHOD OF FREQUENCY SYNTHESIS FOR FAST SWITCHING

Frequency divider with a configurable dividing ratio

RAM based implementation for scalable, reliable high speed event counters

Method of frequency synthesis for fast switching

Apparatus for adjusting resistance value of a driver in a semiconductor integrated circuit

Circuit structure for timer counter and electrical device using the same

Deserializer, related method, and clock frequency divider

System and method for managing counters

Method of frequency synthesis for fast switching

Wide-band frequency synthesizer for zero-IF WLAN radio transceiver and method thereof

Ring oscillator based RC calibration circuit

Circuit and method for compensating noise

IC and a method for flexible integer and fractional divisions

Half-integer frequency dividers that support 50% duty cycle signal generation