221380 ⎘
Circuits for generating electric pulses; Monostable, bistable or multistable circuits; Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback; Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS
#2METHOD FOR FORMING A TIMING CIRCUIT ARRANGEMENTS FOR FLIP-FLOPS
#3Method for forming a timing circuit arrangements for flip-flops
#4Timing circuit arrangements for flip-flops
#5Apparatus for and method of range sensor based on direct time-of-flight and triangulation
#6Circuit including flip-flop and control element
#7High speed voltage level translator including an automatically bootstrapped cascode driver
#8Apparatus for and method of range sensor based on direct time-of-flight and triangulation
#9Voltage translator using low voltage power supply
#10Ultra-Low Power Static State Flip Flop
#11Solid-state imaging apparatus, method for driving solid-state imaging apparatus, and electronic equipment
#12Ultra-low power static state flip flop
#13Power efficient voltage level translator circuit
#14Apparatus for and method of range sensor based on direct time-of-flight and triangulation
#15Latch circuit
#16Apparatuses, methods, and circuits including a duty cycle adjustment circuit
#17Latch circuit with a bridging device
#18Flip-flop for low swing clock signal
#19Latch circuit with a bridging device
#20Latch circuit and clock control circuit
#21LOW POWER LATCH USING MULTI-THRESHOLD VOLTAGE OR STACK-STRUCTURED TRANSISTOR
#22Flip-flop for low swing clock signal
#23Transfer circuit, nonvolatile semiconductor device using the same, and transfer method of the same
#24Flip-flop circuit with internal level shifter
#25Data latch circuit, driving method of the data latch circuit, and display device
#26Flip-flop circuit with internal level shifter
#27Latch and DFF design with improved soft error rate and a method of operating a DFF
#28Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme
#29Slave latch controlled retention flop with lower leakage and higher performance
#30Programmable I/O cell capable of holding its state in power-down mode
#31Flip-flops and electronic digital circuits including the same
#32Digital Voltage Level Shifter
#33Contention-free keeper circuit and a method for contention elimination
#34Programmable I/O cell capable of holding its state in power-down mode
#35Source drive circuit
#36Data latch circuit, driving method of the data latch circuit, and display device
#37Level shift circuit for use in semiconductor device
#38Soft-error rate improvement in a latch
#39Programmable level shifter for wide range operation purpose
#40Liquid crystal display apparatus having level conversion circuit
#41Hybrid pass gate level converting dual supply sequential circuit
#42Source drive circuit, latchable voltage level shifter and high voltage flip-flop
#43Flip-flops, shift registers, and active-matrix display devices
#44Level shifter and flat panel display
#45Low power, up full swing voltage CMOS bus receiver
#46Level shifter circuit