INTER-LANE SKEW COMPENSATION METHOD

IN SITU DELAY MEASUREMENTS ON INTEGRATED CIRCUITS USING LIVE DATA AND PULSE WIDTH MODULATION

Pipeline clock driving circuit, computing chip, hashboard, and computing device

TECHNIQUES FOR DUTY CYCLE CORRECTION

Reduced-power dynamic data circuits with wide-band energy recovery

Low power signaling interface

Clockless time-to-digital converter

Signal output circuit and circuit for outputting delayed signal

Pulse generation circuit and stagger pulse generation circuit

Semiconductor device

Deskew circuit for differential signal

Reduced-power dynamic data circuits with wide-band energy recovery

Clockless time-to-digital converter

Linear low side recycling modulation

Synchronous signaling interface with over-clocked timing reference

SoC supply droop compensation

Clock generator

Harmonic multiplier architecture

Semiconductor integrated circuit and signal processing method

Low power signaling interface

Semiconductor device

Input buffer circuit

Method for synchronizing commutated control circuits controlled by PWM control signals

Set and reset pulse generator circuit

Oscillator and clock generator

Input buffer circuit

Signal driver slew rate control

CLOCK-DISTRIBUTION DEVICE OF IC AND METHOD FOR ARRANGING CLOCK-DISTRIBUTION DEVICE

Semiconductor device

SoC supply droop compensation

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Delay line with short recovery time

Signal driver slew rate control

Efficient duty-cycle balanced clock generation circuit for single and multiple-phase clock signals

Buffer circuit, semiconductor integrated circuit, and system including the buffer circuit

Low power clock buffer circuit for integrated circuit with multi-voltage design

Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals

Circuit for generating at least two rectangular signals with adjustable phase shift and use of said circuit

Clock generation system with dynamic distribution bypass mode

Quadrature divider

Semiconductor devices and semiconductor systems including the same

Wireless transmission apparatus, phase compensating apparatus and phase compensating method thereof

Asynchronous output protocol

System and method for reducing cross coupling effects

Finite impulse response filter for producing outputs having different phases

Partial response receiver and related method

2-phase switched capacitor flash ADC

Tunable clock system

Electronic device and system that initializes logic circuits at different times by sequentially delaying a power up signal to a plurality of internal circuit blocks

Voltage level shifter module

Clock generation system with dynamic distribution bypass mode

Semiconductor device

System for and method of combining CMOS inverters of multiple drive strengths to create tune-able clock inverters of variable drive strengths in hybrid tree-mesh clock distribution networks

Cross-conduction detector for switching regulator

H-bridge gate control circuit

Multi-phase generator

Multi-stage delay-locked loop phase detector

2-phase switched capacitor flash ADC

Phase splitter

Method and system for multiplexing low frequency clocks to reduce interface count

Method and apparatus for a clock and signal distribution network for a 60 GHz transmitter system

Phase Shift Generating Circuit

Reconfigurable and auto-reconfigurable resonant clock

Mechanisms for clock gating

Circuit and method for generating periodic control signals, and microscope and method for controlling a microscope

OCTAL CLOCK PHASE INTERPOLATOR ARCHITECTURE

Data driver, display panel driving device, and display device

SYSTEM AND METHOD FOR REDUCING CROSS COUPLING EFFECTS

Semiconductor device

Finite impulse response filter for producing outputs having different phases

Semiconductor device generating complementary output signals

Semiconductor device

Controlled clock phase generation

Semiconductor device including analog circuit and digital circuit

Partial response receiver and related method

Clock conditioning circuit

Phase shift generating circuit

Phase shifter

System and method for effectively implementing an IQ generator

Low-Phase Noise Low-Power Accurate I/Q Generator Using A Dynamic Frequency Divider

Delay locked loop circuit for semiconductor memory apparatus

System and method for combining a plurality of signals of various phases having a wide frequency range

Non-latching enveloping curves generator

Pulse generator, optical disk writer and tuner

Input enable/disable circuit

Method and apparatus for generating and controlling a multiphase clock

Method and apparatus for generating a multiphase clock

Method and apparatus for generating and controlling a quadrature clock

Method and apparatus for generating a quadrature clock

Serializer clock delay optimization

Signal transmission circuit and power supply line

Internal/external clock selection circuit and method of operation