Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit

Receiver and electronic device using the same

Clock pulse generator apparatus with reduced jitter clock phase

Delay circuit with timing adjustment function

Clock generation apparatus

Clock deskewing method, apparatus, and system

High-speed divider with pulse-width control

Apparatus and method for avoiding steady-state oscillations in the generation of clock signals

Apparatus and method for tuning center frequency of a filter

Phase shifter

PLL TRANSIENT RESPONSE CONTROL SYSTEM AND COMMUNICATION SYSTEM

Duty cycle corrector

Complex band-pass filter

Method for improving the timing resolution of DLL controlled delay lines

DLL circuit and test method thereof

Delay locked loop circuit

DLL circuit having two input standard clocks, clock signal generation circuit having the DLL circuit and clock signal generation method

Delayed Locked Loop Circuit

Clock generator and clock recovery circuit utilizing the same

Local oscillator with injection pulling suppression and spurious products filtering

Phase adjustment circuit

Delay locked loop in synchronous semiconductor memory device and driving method thereof

Delay locked loop circuit

Delay locked loop circuit

DLL driver control circuit

Delay locked loop circuit

Delay locked loop circuit

Clock signal generating and distributing apparatus

Timing vernier using a delay locked loop

Pulse generating circuit, electronic device using this pulse generating circuit, cellular phone set, personal computer, and information transmitting method using this circuit

Clock generation circuit and clock generation method

Clock multipliers using filter bias of a phase-locked loop and methods of multiplying a clock

Dynamic bus inversion method and system

Bit-deskewing IO method and system

Circuit arrangement for generating a reference signal

Adaptive equalizer

Digital control oscillator

Systems, apparatuses and methods for synchronizing clock signals

Delay stabilization circuit and semiconductor integrated circuit

Semiconductor memory device with delay section

Phase controlled oscillator circuit with input signal coupler

Multi-phase clock signal generator and method having inherently unlimited frequency capability

Delay locked loop for controlling duty rate of clock

PLL circuit configured to distribute its loop control signal to CDR circuits

Method and apparatus for digital phase generation at high frequencies

Delay locked loop circuitry for clock delay adjustment

Variable delay circuit

Circuits and methods of generating and controlling signals on an integrated circuit

Multi-phase clock signal generator and method having inherently unlimited frequency capability

Semiconductor device and voltage-controlled oscillation circuit

Delay stabilization circuit and semiconductor integrated circuit

Transconductance / C complex band-pass filter

Receiving apparatus

Apparatus for driving output signals from DLL circuit

Clock and data recovery apparatus and method thereof

Digital circuit having delay circuit for adjustment of clock signal timing

Delay locked loop and semiconductor memory device having the same

Circuit having delay locked loop for correcting off chip driver duty distortion

Phase controlled high speed interfaces

Clock generation apparatus

Circuit and method for recovering a carrier

Test circuit for delay lock loops

Method and apparatus for synchronizing clock timing between network elements

Spread spectrum clock generator

Method and apparatus for calibrating a delay line

Optical driver including a multiphase clock generator having a delay locked loop (DLL), optimized for gigahertz frequencies

CMOS burst mode clock data recovery circuit using frequency tracking method

Digital duty cycle corrector for multi-phase clock application

Device for the regulated delay of a clock signal

Device for setting a clock delay

Timing vernier using a delay locked loop

Method and apparatus for digital phase generation at high frequencies

Spread spectrum clock generator

Digital duty cycle corrector

Phase splitter using digital delay locked loops

Jitter and skew suppressing delay control apparatus

Filter control apparatus and filter system

Low power PLL for PWM switching digital control power supply

PLL circuit and frequency setting circuit using the same

Self calibration of continuous-time filters and systems comprising such filters

Semiconductor device, semiconductor system, and digital delay circuit

Synchronization circuit and synchronization method

Phase controlled oscillator circuit with input signal coupler

DLL circuit with delay equal to one clock cycle

Dynamic copy window control for domain expansion reading

Method and apparatus for tenderizing meat

Time of flight system on a chip

Locked loop with dual rail regulation

Locked loop circuit with clock hold function

Integrated electronic circuit comprising a tunable resonator

Integrable phase-locked loop including an acoustic resonator

Integrable amplitude-locked loop including an acoustic resonator

System with dual rail regulated locked loop

PLL circuit

Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process

High precision continuous time gC BPF tuning

Delay circuit with timing adjustment function

Delay signal generator and recording pulse generator

Integrable acoustic resonator and method for integrating such resonator

Filter apparatus including slave gm-C filter with frequency characteristics automatically tuned by master circuit

Switched capacitor circuit compensation apparatus and method

Programmable direct interpolating delay locked loop

Speed-locked loop to provide speed information based on die operating conditions

Delayed locked loop in semiconductor memory device and its control method

Timing vernier using a delay locked loop

Timing comparator, data sampling apparatus, and testing apparatus

Dummy delay line based DLL and method for clocking in pipeline ADC

Self-tuning varactor system

Variable delay circuit

Clock recovery circuit and communication device

Clock circuitry on plural integrated circuits

Phase controlled high speed interfaces

Phase-locked loop bandwidth calibration circuit and method thereof

Analog equalizer

Method and apparatus for numeric optimization of the control of a delay-locked loop in a network device

Digital phase-locked loop circuit

Percent-of-clock delay circuits with enhanced phase jitter immunity

Direct conversion tuner capable of receiving digital television signals in UHF band and VHF band

System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits

High frequency signal receiver

Digitally controlled tuner circuit

Clock divider of delay locked loop

Precision closed loop delay line for wide frequency data recovery

Interlaced delay-locked loops for controlling memory-circuit timing

Receiver and its tracking adjusting method

Register controlled delay locked loop with reduced delay locking time

System with phase jumping locked loop circuit

Clock alignment system having a dual-loop delay-locked loop

Ring oscillator based RC calibration circuit

Quadrature delay locked loops

Phase-detecting method and circuit for testing a delay locked loop/delay line

Phase stabilization for a frequency multiplier

Voltage-controlled oscillator and phase locked loop having voltage-controlled oscillator

Delta-sigma modulator having expanded fractional input range

Programmable digital sigma delta modulator

Broadband phase locked loop for multi-band millimeter-wave 5G communication

DLL circuit having variable clock divider

Circuit and method for compensating noise

Inverter-based filter biasing with ring oscillator-based supply regulation

Deterministic jitter removal using a closed loop digital-analog mechanism

System and method for controlling a phase lock loop

Methods and apparatus for synchronizing operations using separate asynchronous signals

Techniques for generating clock signals using oscillators

Frequency-locked voltage regulated loop

System and method to speed up PLL lock time on subsequent calibrations via stored band values

Fractional-N phase-locked loop with reduced jitter

Integrated circuits having low power, low interference and programmable delay generators therein and methods of operating same

Apparatus and methods for using tuning information to adaptively and dynamically modify the parameters of an RF signal chain

Buffer circuit for voltage controlled oscillator

Time to digital converter with successive approximation architecture

Synchronization circuit and semiconductor apparatus using the same

System and method for synchronizing local oscillators

Superconducting digital phase rotator