CALIBRATION FOR A RECEIVER BY USING NEIGHBORING RECEIVE PATHS

Power system and method for monitoring a working environment of a monitored circuit and adjusting a working voltage of the monitored circuit

DEADLOCK RECOVERY CIRCUIT AND DEADLOCK RECOVERY METHOD, AND PLL CIRCUIT INCLUDING THE SAME

Oscillator circuit, corresponding radar sensor, vehicle and method of operation

Element having antenna array structure

Oscillator circuit, corresponding radar sensor, vehicle and method of operation

Phase locked loop generating adaptive driving voltage and related operating method

Fast lock phase-locked loop circuit for avoiding cycle slip

Element having antenna array structure

Oscillator circuit, corresponding radar sensor, vehicle and method of operation

Frequency synthesizer with dynamically selected level shifting of the oscillating output signal

Wide-range local oscillator (LO) generators and apparatuses including the same

Method and apparatus for determining a clock frequency for an electronic processor

Phase control oscillator

Wide-range local oscillator (LO) generators and apparatuses including the same

Generation of fast frequency ramps

Phase-locked loop and frequency synthesizer

Phase tracking receiver

Voltage controlled oscillator and phase locked loop comprising the same

Auto frequency calibration method

Data processing device

Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock

Auto frequency calibration for a phase locked loop and method of use

Electronic circuit and control method

Coarse lock detector

Apparatus and method for generating an oscillating output signal

Auto frequency calibration for a phase locked loop and method of use

Digital phase lock loop and method thereof

Clock and data recovery (CDR) architecture and phase detector thereof

Frequency tuning circuit, phase-locked loop circuit, communication apparatus, and storage apparatus

Phase locked loop

CDR with sigma-delta noise-shaped control

Coarse lock detector

Coarse lock detector and delay-locked loop including the same

PLL circuit, and radio communication apparatus equipped with same

Method and apparatus for correcting phase offset errors in a communication device

Phase-locked loop circuit

PLL FREQUENCY SYNTHESIZER

Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency

Phase-locked loop start up circuit

PLL CIRCUIT

Semiconductor device and operating method thereof

PLL loop able to recover a synchronisation clock rhythm comprising a temporal discontinuity

Reduction in the acquisition duration of a phase-locked loop able to reconstitute a synchronisation signal transmitted over an IP network

PLL circuit

System and method for implementing a digital phase-locked loop

Control circuitry

Phase detector circuitry

Frequency synthesizer and method for controlling same

Look loop circuit and method having improved lock time

Phase synchronization circuit and receiver having the same

System and method for implementing a digital phase-locked loop

PLL circuit

Digital phase-locked loop operating based on fractional input and output phases

Phase locked loop and method for operating the same

PLL with controllable bias level

Communication semiconductor integrated circuit device and wireless communication system

PLL control circuit of optical disc apparatus, and recording medium having recorded thereon program for controlling the optical disc apparatus

Frequency tuning range extension and modulation resolution enhancement of a digitally controlled oscillator

Expanded pull range for a voltage controlled clock synthesizer

Voltage-controlled oscillator with stable gain over a wide frequency range

Phase-lock loop, method for frequency switching in a phase-lock loop, and use of said phase-lock loop

Phase locked loop having cycle slip detector capable of compensating for errors caused by cycle slips

Communication semiconductor integrated circuit device and wireless communication system

Startup/yank circuit for self-biased phase-locked loops

Adjustable lock-in circuit for phase-locked loops

Smart lock-in circuit for phase-locked loops

Phase-locked loop circuit

Phase-locked loop having dynamically adjustable up/down pulse widths

Semiconductor integrated circuit for wireless communication

Burst mode receiver based on charge pump PLL with idle-time loop stabilizer

PLL synthesizer

Yank detection circuit for self-biased phase locked loops

System and method to speed up PLL lock time on subsequent calibrations via stored band values