222717 β
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits; Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit using single parity bit
SEMICONDUCTOR DEVICE AND COMMUNICATION SYSTEM
#2CODING SCHEME FOR INSERTING INFORMATION BIT INTO 8B/10B CODED DATA STREAM
#3DELAYED SNOOP FOR MULTI-CACHE SYSTEMS
#4MULTICORE SHARED CACHE OPERATION ENGINE
#5CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#6VIRTUAL NETWORK PRE-ARBITRATION
#7METHOD AND DEVICE FOR SIMPLIFIED SUCCESSIVE CANCELLATION LIST DECODING OF POLARIZATION-ADJUSTED CONVOLUTIONAL (PAC) CODES
#8FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY
#9MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
#10PROGRAMMABLE METADATA
#11MULTICORE SHARED CACHE OPERATION ENGINE
#12CONFIGURABLE CACHE FOR COHERENT SYSTEM
#13Iterative error correction in memory systems
#14COMMAND ADDRESS FAULT DETECTION
#15DEFERRED ERROR CODE CORRECTION WITH IMPROVED EFFECTIVE DATA BANDWIDTH PERFORMANCE
#16MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
#17Flash memory apparatus and storage management method for flash memory
#18DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
#19Parallel system to calculate low density parity check
#20Iterative decoder with a dynamic maximum stop condition
#21Command address fault detection
#22Multicore shared cache operation engine
#23Error correction method, error correction circuit and electronic device applying the same
#24Configurable cache for coherent system
#25METHOD AND APPARATUS FOR TRANSMITTING DATA CONCURRENTLY WITH A PULSE-ENCODED SIGNAL
#26Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#27Syndrome calculation for error detection and error correction
#28Correlation-based hardware sequence for layered decoding
#29Communication throughput despite periodic blockages
#30Iterative error correction in memory systems
#31Dynamic frozen bits and error detection for polar codes
#32Method for generating burst error correction code, device for generating burst error correction code, and recording medium storing instructions to perform method for generating burst error correction code
#33Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code circuit
#34SYSTEM AND METHOD FOR DECODING ENCODED MESSAGES IN A WIRELESS COMMUNICATION SYSTEM
#35Memory system
#36Single-cycle byte correcting and multi-byte detecting error code
#37Syndrome calculation for error detection and error correction
#38Forward error correction coding using a tree structure
#39Programmable metadata
#40Method and apparatus for encoding and decoding polar code
#41Storage device and control method for storage device
#42Multi-rate ECC parity for fast SLC read
#43Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#44Multicore, multibank, fully concurrent coherence controller
#45CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#46Cyclic redundancy check, CRC, decoding using the inverse CRC generator polynomial
#47DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
#48MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPECULATION AWARE SHARED MEMORY AND INTERCONNECT
#49Error detection in communication systems using polar coded data transmission
#50Configurable cache for multi-endpoint heterogeneous coherent system
#51Communication throughput despite periodic blockages
#52Flash memory apparatus and storage management method for flash memory
#53Forward error correction coding using a tree structure
#54Method and system for providing minimal aliasing error correction code
#55Delayed snoop for improved multi-process false sharing parallel thread performance
#56Multicore shared cache operation engine
#57Configuring iterative error correction parameters using criteria from previous iterations
#58Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#59Multi-processor bridge with cache allocate awareness
#60Processing-in-memory (PIM) devices
#61Processing-in-memory (PIM) devices
#62Processing-in-memory (PIM) devices
#63MULTICORE SHARED CACHE OPERATION ENGINE
#64Decoding method, memory storage device, and memory controlling circuit unit
#65Processing-in-memory (PIM) devices
#66System and method for decoding encoded messages in a wireless communication system
#67Configuring iterative error correction parameters using criteria from previous iterations
#68Bit block stream bit error detection method and device
#69Deferred error code correction with improved effective data bandwidth performance
#70Communication throughput despite periodic blockages
#71Successive cancellation list-based decoder and decoding method thereof
#72System and method for decoding encoded messages in a wireless communication system
#73Network access node and a client device for content type indication
#74Memory system, packet protection circuit, and CRC calculation method
#75Intelligent controller and sensor network bus, system and method including an error avoidance and correction mechanism
#76Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#77Encoding and decoding method and terminal
#78Method for constructing parity-check concatenated polar codes and apparatus therefor
#79Flash memory apparatus and storage management method for flash memory
#80Deferred error code correction with improved effective data bandwidth performance
#81Methods and apparatuses for error correction
#82Rate matching performing method for LDPC code and communication device therefor
#83Method and apparatus for encoding and decoding data in memory system
#84Polar code encoding method and apparatus, polar code decoding method and apparatus, and device
#85LPWAN communication protocol design with turbo codes
#86Distributed error detection and correction with hamming code handoff
#87Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect
#88Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#89Credit aware central arbitration for multi-endpoint, multi-core system
#90Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#91Multi-power-domain bridge with prefetch and write merging
#92Multicore, multibank, fully concurrent coherence controller
#93Delayed snoop for improved multi-process false sharing parallel thread performance
#94Multicore shared cache operation engine
#95Configurable cache for multi-endpoint heterogeneous coherent system
#96Multi-processor bridge with cache allocate awareness
#97Multicore shared cache operation engine
#98Bit block stream bit error detection method and device
#99Dynamic frozen bits and error detection for polar codes
#100Device for verifying data transmissions and method using the same
#101Encoding and decoding method and terminal
#102Error correction coded binary array
#103Apparatus and method for encoding and decoding using polar code in wireless communication system
#104Enhanced polar code constructions by strategic placement of CRC bits
#105Error detection in communication systems using polar coded data transmission
#106Method and apparatus of using parity to detect random faults in memory mapped configuration registers
#107Flash memory apparatus and storage management method for flash memory
#108Memory device including parity error detection circuit
#109Encoding and decoding using a polar code
#110Method and system for advanced outer coding
#111Semiconductor device including error correction code unit that generates data block matrix including plural parity blocks and plural data block groups diagonally arranged, and methods of operating the same
#112Physical layer frame format for WLAN
#113Gel codeword structure encoding and decoding method, apparatus, and related device
#114Methods and apparatuses for error correction
#115Systems and methods for improved error correction in a refreshable memory
#116Data storage error protection
#117Method and apparatus for decoding three-dimensional turbo product code based on crossing layers
#118Data conversion apparatus
#119Transmission method and processing method for bitstream in wireless communication system
#120RFID Systems with Low Complexity Implementation and Pallet Coding Error Correction
#121Enhanced polar code constructions by strategic placement of CRC bits
#122Transmitting node, a receiving node and methods therein for providing enhanced channel coding
#123Memory controller, memory system including the same and operating method thereof
#124DATA PROCESSING SYSTEM AND DATA PROCESSING APPARATUS
#125Redundant bytes utilization in error correction code
#126BIT-ERROR RATE FALSE POSITIVE DETECTION SYSTEM AND METHOD
#127Methods for Recovering RFID Data Based Upon Probability Using an RFID Receiver
#128Enhanced polar code constructions by strategic placement of CRC bits
#129Memory device including parity error detection circuit
#130Flash memory apparatus and storage management method for flash memory
#131Flexible erasure coding with enhanced local protection group structures
#132Packet transmission/reception apparatus and method using forward error correction scheme
#133Data error correcting method and device, and computer storage medium
#134Turbo product codes for NAND flash
#135Apparatus and method for turbo product codes
#136Two-way parity error detection for advanced encryption standard engines
#137Using error correcting codes for parity purposes
#138Using error correcting codes for parity purposes
#139Positioning signal receiving method and positioning signal receiving device
#140Physical layer frame format for WLAN
#141Communication system, communication unit, and communication method
#142Systems and methods for encoding and decoding of check-irregular non-systematic IRA codes
#143Methods, apparatus, and systems for coding with constrained interleaving
#144Methods for recovering RFID data based upon probability using an RFID receiver
#145Encoding method and encoding apparatus in a wireless communications system
#146Method and device for write abort protection
#147Inband management of ethernet links
#148Storage device and data latch timing adjustment method
#149Methods, apparatus, and systems for coding with constrained interleaving
#150Encoding and decoding using constrained interleaving
#151Methods, apparatus, and systems for coding with constrained interleaving
#152Circuits, integrated circuits, and methods for interleaved parity computation
#153Impaired carrier coding
#154RFID systems with low complexity implementation and pallet coding error correction
#155System and method for mitigating burst noise in a communications system
#156Systems and methods for encoding and decoding of check-irregular non-systematic IRA codes
#157Data error-detection system and data error-detection method thereof
#158Method and apparatus for decoding received packets in broadcasting and communication system
#159Content addressable memory continuous error detection with interleave parity
#160System and method for detecting errors in audio data
#161Detecting data transmission errors in an inter-integrated circuit (βICβ) system
#162Storage control apparatus, storage system, and storage control method
#163Lost real-time media packet recovery
#164Circuits, integrated circuits, and methods for interleaved parity computation
#165Error detection and correction of a data transmission
#166Error detection and correction of a data transmission
#167Methods for recovering RFID data based upon probability using an RFID receiver
#168Architecture and control of reed-solomon error-correction decoding
#169Transmitter, encoding apparatus, receiver, and decoding apparatus
#170Architecture and control of Reed-Solomon error-correction decoding
#171Command control circuit, integrated circuit having the same, and command control method
#172Rendering data write errors detectable
#173Parity look-ahead scheme for tag cache memory
#174Application layer FEC framework for WiGig
#175Method and apparatus for storing data
#176Interleaved correction code transmission
#177Systems and methods for utilizing circulant parity in a data processing system
#178Constant amplitude encoding apparatus and method for code division multiplexing communication system
#179Storage device with flash memory and data storage method
#180RFID receiver
#181Error pattern generation for trellis-based detection and/or decoding
#182CHANNEL ENCODING AND DECODING APPARATUSES AND METHODS
#183Decoding techniques for correcting errors using soft information
#184Method and apparatus for error compensation
#185Soft error correction in sleeping processors
#186Ensuring data consistency
#187System and method for mitigating burst noise in a communications system
#188Architecture and control of reed-solomon error identification and evaluation
#189METHOD FOR SERIAL ASYNCHRONOUS TRANSMISSION OF DATA IN AN ARRAGEMENT FOR THE MONITORING, CONTROLLING, AND REGULATING AN OPERATIONAL CONTROL FACILITY OF BUILDING
#190Encoding device, decoding device, encoding/decoding device, and recording/reproducing device
#191DATA TRANSMISSION METHOD
#192Architecture and control of reed-solomon error-correction decoding
#193Architecture and control of Reed-Solomon error-correction decoding
#194Architecture and control of Reed-Solomon list decoding
#195Error correction method and apparatus
#196Nonvolatile memory device, system, and method providing fast program and read operations
#197Communication apparatus communicating with different bit rates
#198RFID system with low complexity implementation and pallet coding error correction
#199Decoder and reproducing device
#200Decoding device, encoding/decoding device and recording/reproducing device
#201Method and apparatus for error compensation
#202Reliability metric generation for trellis-based detection and/or decoding
#203Communication channel with Reed-Solomon encoding and single parity check
#204SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH BUS DIAGNOSTIC FEATURES
#205SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR PROVIDING A TWO-BIT SYMBOL BUS ERROR CORRECTING CODE WITH BUS TIMING IMPROVEMENTS
#206Transmitter for transmitting information data and receiver for receiving information data
#207Encoding method, transmitter, network element and communication terminal
#208Systems and methods for error reduction associated with information transfer
#209Method for lost packet reconstruction and device for carrying out said method
#210RFID receiver
#211Decoding techniques for correcting errors using soft information
#212Apparatus and method for detecting data error
#213Method and apparatus for providing a read channel having combined parity and non-parity post processing
#214Error correction using iterating generation of data syndrome
#215Data detection and decoding system and a method of detecting and decoding data
#216Flexible rate and punctured zigzag codes
#217Running digital sum coding system
#218Method and apparatus for communications using turbo like codes
#219Turbo product code implementation and decoding termination method and apparatus
#220Cyclic redundancy check based message passing in turbo product code decoding
#221Method of forward error correction
#222Transmission apparatus and method, reception apparatus and method, storage medium, and program
#223Device and method of applying a parity to encrypt data for protection
#224In-line wire error correction
#225Codeword format for data storage
#226Error correction method, error correction circuit and electronic device applying the same
#227Exact ber reporting in the presence of CRC termination
#228Externalizing inter-symbol interference data in a data channel
#229Managing defective bitline locations in a bit flipping decoder
#230Methods and systems for short error event correction in storage channel applications
#231Efficient determination of parity bit location for polar codes
#232Method and apparatus for error detection and correction
#233System and method for memory control having address integrity protection for error-protected data words of memory transactions
#234Parallel-to-parallel conversion and reordering of a block of data elements