222757 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits; Linear codes; Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials Finite field arithmetic processing
Secure Multi-Rail Control for Sparsely Encoded Signals
#2Coding circuit and memory device including the same
#3Bose-Chadhuri-Hocquenghem (BCH) encoder and method for generating a BCH signal for navigation signal
#4Cryptographic computer machines with novel switching devices
#5Storage error correction using cyclic-code based LDPC codes
#6Integrated circuit
#7Combined SBox and inverse SBox cryptography
#8Using parity data for concurrent data authentication, correction, compression, and encryption
#9Forward error correction including correction capability determinations based on symbol errors of error bit based codewords
#10Encoder with mask based galois multipliers
#11Apparatus and method for multi-code distributed storage
#12Error correction using cyclic code-based LDPC codes
#13Using parity data for concurrent data authentication, correction, compression, and encryption
#14AES/CRC engine based on resource shared galois field computation
#15Forward error correction (FEC) emulator
#16One-sub-symbol linear repair schemes
#17Encoding method, encoder, and decoder for dynamic power consumption control
#18Reduced latency error correction decoding
#19SLIDING WINDOW LIST DECODER FOR ERROR CORRECTING CODES
#20Forward error correction (FEC) emulator
#21List decode circuits
#22List decode circuits
#23Using parity data for concurrent data authentication, correction, compression, and encryption
#24RS error correction decoding method
#25Decoding apparatus, decoding method and program
#26Forward error correction (FEC) emulator
#27Generating cryptographic checksums
#28Erasure code data protection and recovery computation system and method
#29Sliding window list decoder for error correcting codes
#30ECC circuit, storage device and memory system
#31Error correction using cyclic code-based LDPC codes
#32Using parity data for concurrent data authentication, correction, compression, and encryption
#33Processor and method for executing wide operand multiply matrix operations
#34Sliding window list decoder for error correcting codes
#35Multi-code Chien's search circuit for BCH codes with various values of m in GF(2)
#36Chien search device, storage device, and chien search method
#37Low complexity partial parallel architectures for Fourier transform and inverse Fourier transform over subfields of a finite field
#38N-valued shift registers with inverter reduced feedback logic functions
#39Methods, circuits, systems and computer executable instruction sets for providing error correction of stored data and data storage devices utilizing same
#40Method and controller for processing data multiplication in RAID system
#41Error correction code circuit and memory device including the same
#42Error location search circuit, and error check and correction circuit and memory device including the same
#43Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
#44Galois field arithmetic operation circuit and memory device
#45Processor for executing wide operand operations using a control register and a results register
#46PARITY PREDICTOR, CARRY-LESS MULTIPLIER AND ARITHMETIC OPERATION PROCESSING APPARATUS
#47Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
#48Methods and Systems for Rapid Error Location in Reed-Solomon Codes
#49Methods and apparatus in alternate finite field based coders and decoders
#50Apparatus and method of processing polynomials
#51Error correction mechanisms for flash memories
#52Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)
#53Methods and systems for rapid error correction of Reed-Solomon codes
#54High-speed and agile encoder for variable strength long BCH codes
#55Methods and Apparatus in Alternate Finite Field Based Coders and Decoders
#56Polynomial division
#57Redundant code generation method and device, data restoration method and device, and raid storage device
#58EFFICIENT IMPLEMENTATION OF A KEY-EQUATION SOLVER FOR BCH CODES
#59Modulus-based error-checking technique
#60Array form reed-solomon implementation as an instruction set extension
#61Determining a message residue
#62High speed syndrome-based FEC encoder and system using same
#63Processor for executing multiply matrix instructions requiring wide operands
#64Computer system for executing switch and table translate instructions requiring wide operands
#65Processor architecture with wide operand cache
#66Method for performing computations using wide operands
#67Data processing method and computer system medium thereof
#68Processor and method for executing instructions requiring wide operands for multiply matrix operations
#69System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic
#70Low area architecture in BCH decoder
#71System and software for performing matrix multiply extract operations
#72System and method for performing reed-solomon encoding
#73Methods and apparatus for improved error and erasure correction in a Reed-Solomon date channel
#74Error correction in multi-valued (p,k) codes
#75Error correction by symbol reconstruction in binary and multi-valued cyclic codes
#76CONFIGURABLE INTERFACE FOR CONNECTING VARIOUS CHIPSETS FOR WIRELESS COMMUNICATION TO A PROGRAMMABLE (MULTI-)PROCESSOR
#77Combined encoder/syndrome generator with reduced delay
#78Error correction using finite fields of odd characteristics on binary hardware
#79Method and controller for processing data multiplication in RAID system
#80Decoder architecture for Reed Solomon codes
#81Multiply redundant raid system and XOR-efficient method and apparatus for implementing the same
#82Techniques for performing Galois field logarithms for detecting error locations that require less storage space
#83Techniques for performing reduced complexity galois field arithmetic for correcting errors
#84Semiconductor memory device
#85Condensed Galois field computing system
#86Low complexity bit-parallel systolic architecture for computing C+AB, AB, C+AB2 or AB2 over a class of GF (2m)
#87System and method for implementing a Reed Solomon multiplication section from exclusive-OR logic
#88High speed syndrome-based FEC encoder and system using same
#89Forward Chien search type Reed-Solomon decoder circuit
#90Method of soft-decision decoding of Reed-Solomon codes
#91Methods and apparatus for coding and decoding data using Reed-Solomon codes
#92Single error Reed-Solomon decoder
#93Reed-solomon code encoder and decoder
#94System and method for encoding using multiple linear feedback shift registers
#95Circuit enabling and a method of generating a product in a decoder circuit