222789 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques Interleaver with an interleaving rule not provided for in the subgroups -
EFFICIENT INTERLEAVER DESIGN FOR POLAR CODES
#2BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 7/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME
#3Data coding processing method and apparatus, storage medium, and electronic device
#4Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
#5Efficient interleaver design for polar codes
#6Efficient interleaver design for polar codes
#7Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
#8Data processing device and data processing method
#9Storage error correction using cyclic-code based LDPC codes
#10Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
#11Data processing device and data processing method
#12Data processing device and data processing method
#13INTERMEDIATE TRANSFER UNIT THAT BUFFERS TENSION THAT BACKUP ROLLER RECEIVES FROM INTERMEDIATE TRANSFER BELT, AND IMAGE FORMING APPARATUS
#14Time varying data permutation apparatus and methods
#15Transmission method and reception device
#16Efficient interleaver design for polar codes
#17Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
#18Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
#19Transmission method and reception device
#20Error correction using cyclic code-based LDPC codes
#21Data processing device and data processing method
#22Data processing device and data processing method
#23Data storage device encoding and interleaving codewords to improve trellis sequence detection
#24Data storage device encoding and interleaving codewords to improve trellis sequence detection
#25Time varying data permutation apparatus and methods
#26Efficient interleaver design for polar codes
#27Data processing device and data processing method
#28Cyclically interleaved XOR array for error recovery
#29Error correction using cyclic code-based LDPC codes
#30Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
#31Time varying data permutation apparatus and methods
#32Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
#33DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
#34Polar code rate matching method and polar code rate matching apparatus
#35Polar code rate matching method and apparatus
#36Time and cell de-interleaving circuit and method for performing time and cell de-interleaving
#37Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and quadrature phase shift keying, and bit interleaving method using same
#38Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and quadrature phase shift keying, and bit interleaving method using same
#39Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and quadrature phase shift keying, and bit interleaving method using same
#40Signal processing device and method of performing a pack-insert operation
#41Method and apparatus for performing interleaving in communication system
#42Apparatus and method for transmitting/receiving signal in communication system supporting bit-interleaved coded modulation with iterative decoding scheme
#43Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same
#44Bit-interleaver for an optical line terminal
#45Transmitter and signal processing method thereof
#46Transmitting apparatus, and puncturing method thereof
#47Time varying data permutation apparatus and methods
#48Continuously interleaved error correction
#49Time varying data permutation apparatus and methods
#50Vector-based matching circuit for data streams
#51Time varying data permutation apparatus and methods
#52Continuously interleaved error correction
#53Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
#54Data processing apparatus and method
#55System and method for signaling control information in a mobile communication network
#56System and method for signaling control information in a mobile communication network
#57Interleaving scheme for an LDPC coded 32 APSK system
#58Method and apparatus for adapting a bit interleaver to LDPC codes and modulations under AWGN channel conditions using binary erasure surrogate channels
#59Subwords coding using different encoding/decoding matrices
#60Subwords coding using different interleaving schemes
#61Communications channel parallel interleaver and de-interleaver
#62Encoding method and apparatus
#63Continuously interleaved error correction
#64Pruned bit-reversal interleaver
#65Advanced MIMO interleaving
#66Parallel concatenated code with soft-in soft-out interactive turbo decoder
#67Pruned bit-reversal interleaver
#68De-Interlever That Simultaneously Generates Multiple Reorder Indices
#69BUTTERFLY NETWORK FOR PERMUTATION OR DE-PERMUTATION UTILIZED BY CHANNEL ALGORITHM
#70Data processing apparatus and method for use with a 4K interleaver in a digital video broadcasting (DVB) standard
#71Interleaving of information bits
#72Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
#73Quadratic polynomial permutation (QPP) interleaver providing hardware savings and flexible granularity adaptable to any possible turbo code block size
#74Parallel interleaving apparatus and method
#75Parallel concatenated code with soft-in soft-out interactive turbo decoder
#76Bit interleaver and method of bit interleaving using the same
#77Loading the input memory of an LDPC decoder with data for decoding
#78Interleaver and de-interleaver
#79Network for permutation or de-permutation utilized by channel coding algorithm
#80Methods and apparatus for interleaving in a block-coherent communication system
#81Dynamic minimum-memory interleaving
#82System and method for time diversity
#83Parallel concatenated code with soft-in-soft-out interactive turbo decoder
#84Interleaving of information bits
#85Pruned bit-reversal interleaver
#86System and method for modulation diversity
#87System and method for frequency diversity
#88System and method for providing 3-dimensional joint interleaver and circulation transmissions
#89Methods and apparatus for circulation transmissions for OFDM-based MIMO systems
#90Advanced MIMO interleaving
#91Parallel concatenated code with soft-in soft-out interactive turbo decoder
#92Parallel concatenated code with soft-in soft-out interactive turbo decoder
#93Parallel concatenated code with soft-in soft-out interactive turbo decoder
#94Data storage device encoding and interleaving codewords to improve trellis sequence detection