222794 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques; Internal interleaver for turbo codes Contention or collision free turbo code internal interleaver
Flexible polynomial-based interleaver
#2Turbo decoders with stored column indexes for interleaver address generation and out-of-bounds detection and associated methods
#3Data transmission method, device, and system
#4Self-configurable device for interleaving/deinterleaving data frames
#5HALF PIPELINED TURBO DECODER AND METHOD FOR CONTROLLING THEREOF
#6Device and method for transmitting data using convolutional turbo code (CTC) encoder in mobile communication system
#7Method and apparatus for turbo decoder memory collision resolution
#8Multicore type error correction processing system and error correction processing apparatus
#9Decoding apparatus with de-interleaving efforts distributed to different decoding phases and related decoding method thereof
#10Multi-processing architecture for an LTE turbo decoder (TD)
#11Turbo code parallel interleaver and parallel interleaving method thereof
#12Simplified parallel address-generation for interleaver
#13Calculation Method and Device of Intra-Turbo Code Interleaver
#14Accessing memory during parallel turbo decoding
#15Address generation apparatus and method for quadratic permutation polynomial interleaver
#16Accessing Memory for Data Decoding
#17Reconfigurable interleaver having reconfigurable counters
#18Rate matching device
#19Method and apparatus for parallel de-interleaving of LTE interleaved data
#20Interleaving/de-interleaving method, soft-in/soft-out decoding method and error correction code encoder and decoder utilizing the same
#21RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS
#22Turbo decoding device and communication device
#23Recursive realization of polynomial permutation interleaving
#24Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors
#25ASIP architecture for executing at least two decoding methods
#26Extended turbo interleavers for parallel turbo decoding
#27Turbo interleaver for high data rates
#28Serially concatenated convolutional code decoder with a constrained permutation table
#29Address generation for multiple access of memory
#30METHOD AND APPARATUS FOR CONTENTION-FREE INTERLEAVING USING A SINGLE MEMORY
#31De-interleaving mechanism involving a multi-banked LLR buffer
#32Apparatus of multi-stage network for iterative decoding and method thereof
#33Data interleaving circuit and method for vectorized turbo decoder
#34Method and apparatus for parallel structured Latin square interleaving in communication system
#35Method and device for interleaving data
#36Multiple access for parallel turbo decoder
#37Turbo decoder
#38Method and apparatus for encoding and decoding data
#39Quadratic polynomial permutation (QPP) interleaver providing hardware savings and flexible granularity adaptable to any possible turbo code block size
#40QPP interleaver/de-interleaver for turbo codes
#41Parallel interleaving apparatus and method
#42Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors
#43Method and system for providing a contention-free interleaver for channel coding
#44Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size
#45General and algebraic-constructed contention-free memory mapping for parallel turbo decoding with algebraic interleave ARP (almost regular permutation) of all possible sizes
#46Pre-emptive interleaver address generator for turbo decoders