222797 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques; Interleaver implementations, which reduce the amount of required interleaving memory Interleaver using in-place interleaving, i.e. writing to and reading from the memory is performed at the same memory location
DELAYED SNOOP FOR MULTI-CACHE SYSTEMS
#2MULTICORE SHARED CACHE OPERATION ENGINE
#3CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#4VIRTUAL NETWORK PRE-ARBITRATION
#5MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
#6MULTICORE SHARED CACHE OPERATION ENGINE
#7CONFIGURABLE CACHE FOR COHERENT SYSTEM
#8MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
#9DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
#10Multicore shared cache operation engine
#11Configurable cache for coherent system
#12Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#13Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#14Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#15Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#16Multicore, multibank, fully concurrent coherence controller
#17CREDIT AWARE CENTRAL ARBITRATION FOR MULTI-ENDPOINT, MULTI-CORE SYSTEM
#18DISTRIBUTED ERROR DETECTION AND CORRECTION WITH HAMMING CODE HANDOFF
#19MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPECULATION AWARE SHARED MEMORY AND INTERCONNECT
#20Configurable cache for multi-endpoint heterogeneous coherent system
#21Delayed snoop for improved multi-process false sharing parallel thread performance
#22Multicore shared cache operation engine
#23Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#24Multi-processor bridge with cache allocate awareness
#25MULTICORE SHARED CACHE OPERATION ENGINE
#26Deinterleaver
#27Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#28System, method, and apparatus for interleaving data
#29Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#30Distributed error detection and correction with hamming code handoff
#31Multi-processor, multi-domain, multi-protocol, cache coherent, speculation aware shared memory and interconnect
#32Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure
#33Credit aware central arbitration for multi-endpoint, multi-core system
#34Virtual network pre-arbitration for deadlock avoidance and enhanced performance
#35Multi-power-domain bridge with prefetch and write merging
#36Multicore, multibank, fully concurrent coherence controller
#37Delayed snoop for improved multi-process false sharing parallel thread performance
#38Multicore shared cache operation engine
#39Configurable cache for multi-endpoint heterogeneous coherent system
#40Multi-processor bridge with cache allocate awareness
#41Multicore shared cache operation engine
#42System, method, and apparatus for interleaving data
#43Deinterleaver
#44Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#45Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#46Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#47DE-INTERLEAVING CIRCUIT AND DE-INTERLEAVING METHOD
#48Time interleaver, time deinterleaver, time interleaving method, and time deinterleaving method
#49Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction
#50Variable modulation with LDPC (low density parity check) coding
#51Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
#52Method and device for flexible error correction encoding and corresponding computer program
#53Variable modulation with LDPC (low density parity check) coding
#54Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction
#55Receiving apparatus, receiving method, program, and receiving system
#56True bit level decoding of TTCM (turbo trellis coded modulation) of variable rates and signal constellations
#57De-interleaving mechanism involving a multi-banked LLR buffer
#58Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
#59Method for interleaving data in a communication device
#60In-place data deinterleaving
#61Method and apparatus for memory optimization in MPE-FEC system
#62Variable modulation with LDPC (low density parity check) coding
#63Variable code rate and signal constellation turbo trellis coded modulation codec
#64In-place transformations with applications to encoding and decoding various classes of codes
#65Turbo decoding apparatus and interleave-deinterleave apparatus
#66Interleaver for iterative decoder
#67System and method for interleaving data in a communication device
#68Memory control method for time deinterleaving in DMB receiver
#69Deinterleaving device for digital broadcast receivers having a downsized deinterleaver memory and deinterleaving method thereof
#70Variable modulation with LDPC (low density parity check) coding
#71Interleaver and device for decoding digital signals comprising such an interleaver
#72System and method for interleaving data in a communications device
#73Method, apparatus, and system for deinterleaving data