222843 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Decoding methods or techniques, not specific to the particular type of coding provided for in groups - ; Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code Adaptation to the number of estimated errors or to the channel state
MULTI-CHANNEL DECODER WITH DISTRIBUTED SCHEDULING
#2Error correction code decoder, storage controller and storage device
#3Decoder and data processing device including the same
#4Systems and methods of decoding error correction code of a memory device with dynamic bit error estimation
#5Composite data recovery procedure
#6SYSTEM AND METHOD FOR DECODING ENCODED MESSAGES IN A WIRELESS COMMUNICATION SYSTEM
#7Channel coding method of variable length information using block code
#8Memory system
#9Receiver circuits performing error correction including identification of a most likely error event based on an enable signal indicative of presence of errors
#10Dynamic multi-stage decoding
#11Soft decoding method using LLR conversion table
#12Error correction circuit and method for operating the same
#13Transmitting system and method of processing digital broadcast signal in transmitting system, receiving system and method of receiving digital broadcast signal in receiving system
#14Dynamic multi-stage decoding
#15System and method for decoding encoded messages in a wireless communication system
#16Channel coding method of variable length information using block code
#17Memory system
#18Error correction circuit and method for operating the same
#19Tiered error correction code (ECC) operations in memory
#20Memory system
#21Channel coding method of variable length information using block code
#22Data transmission method, apparatus and storage medium
#23Dynamic multi-stage decoding
#24Conditional forward error correction for network data
#25Dynamic multi-stage decoding
#26Estimating an error rate associated with memory
#27Memory system and control method
#28Systems and methods for decoding error correcting codes
#29Memory system
#30Transmitting system and method of processing digital broadcast signal in transmitting system, receiving system and method of receiving digital broadcast signal in receiving system
#31Channel coding method of variable length information using block code
#32Tiered error correction code (ECC) operations in memory
#33Method and apparatus for data processing in a communication system
#34Transmission method, transmission device, reception method, and reception device
#35Dynamic multi-stage decoding
#36Error correction device, operating method of error correction device, and controller including error correction device
#37Systems and methods for decoding error correcting codes
#38Systems and methods for decoding error correcting codes
#39Memory system and operating method thereof
#40Memory system and method for operating the same
#41Dynamic multi-stage decoding
#42Techniques for correcting data errors in memory devices
#43Low BER hard-decision LDPC decoder
#44Memory system with decoders and method of operating such memory system and decoders
#45Memory system
#46Bit flipping algorithm for providing soft information during hard decision hard decoding
#47Multi-channel decoder with distributed scheduling
#48Data storage apparatus and operating method thereof
#49High performance memory controller
#50Method and apparatus for operating a data storage system
#51Parameterized iterative message passing decoder
#52Method and data storage device to estimate a number of errors using convolutional low-density parity-check coding
#53Estimating an error rate associated with memory
#54Controller, semiconductor memory system and operating method thereof
#55PBCH signal design and efficient continuous monitoring and polar decoding
#56Use of multiple codebooks for programming data in different memory areas of a storage device
#57Memory controller, memory system, and method for controlling memory system
#58Data read method and memory storage device using the same
#59Data processing apparatus
#60Flexible error correction
#61Adaptive bit-flipping decoder based on dynamic error information
#62Low power error correcting code (ECC) system
#63Configurable ECC decoder
#64Decoding method, memory storage device and memory control circuit unit
#65Decoding method, memory storage device and memory control circuit unit
#66Transmitting system and method of processing digital broadcast signal in transmitting system, receiving system and method of receiving digital broadcast signal in receiving system
#67Early selection decoding and automatic tuning
#68Bit flipping algorithm for providing soft information during hard decision hard decoding
#69Transmission method, transmission device, reception method, and reception device
#70Method and data storage device using convolutional low-density parity-check coding with a long page write and a short page read granularity
#71Method and data storage device to estimate a number of errors using convolutional low-density parity-check coding
#72High performance memory controller
#73Progressive effort decoder architecture
#74Channel coding method of variable length information using block code
#75Decoding method, memory storage device and memory control circuit unit
#76LDPC Erasure Decoding for Flash Memories
#77Estimating an error rate associated with memory
#78Method and apparatus for reducing idle cycles during LDPC decoding
#79Methods and systems for maximizing read performance of error detection code
#80Tracking and use of tracked bit values for encoding and decoding data in unreliable memory
#81Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes
#82Channel coding method of variable length information using block code
#83High performance memory controller
#84Estimating an error rate associated with memory
#85GLDPC soft decoding with hard decision inputs
#86Nonvolatile memory refresh
#87Controller, semiconductor memory system, data storage system and operating method thereof
#88Error correction decoder and operation method of the error correction decoder
#89Progressive effort decoder architecture
#90Non-volatile memory controller with error correction (ECC) tuning via error statistics collection
#91Low BER hard-decision LDPC decoder
#92Forward error correction with turbo/non-turbo switching
#93Decoding method, memory storage device and memory controlling circuit unit
#94Transmitting system and method of processing digital broadcast signal in transmitting system, receiving system and method of receiving digital broadcast signal in receiving system
#95Forward error correction (FEC) for local area networks (LANs)
#96Ultra low power (ULP) decoder and decoding processing
#97Reconstructive error recovery procedure (ERP) using reserved buffer
#98Memory controller, storage device, and memory control method
#99Memory controllers and flash memory reading methods
#100Channel coding method of variable length information using block code
#101Data processing apparatus
#102Error correction in memory
#103Decoder with selective iteration scheduling
#104Operating method of error correction code decoder and memory controller including the error correction code decoder
#105Advance clocking scheme for ECC in storage
#106Memory controller
#107Communication device, communication method, and communication program
#108Methods and systems for error-correction decoding
#109Single-bit first error correction
#110Method and device for transmitting frame
#111Inter symbol interference reduction by applying turbo equalization mode
#112Techniques for error correction of encoded data
#113Memory controller and operating method of memory controller
#114Error-correction decoding with reduced memory and power requirements
#115Storage device
#116Techniques associated with error correction for encoded data
#117Decoding device
#118Worker and iteration control for parallel turbo decoder
#119Data independent error computation and usage with decision directed error computation
#120Transmitting system and method of processing digital broadcast signal in transmitting system, receiving system and method of receiving digital broadcast signal in receiving system
#121ADAPTIVE ERROR CORRECTION FOR PHASE CHANGE MEMORY
#122Decoders and methods for decoding convolutional coded data
#123Systems and methods for mis-correction correction in a data processing system
#124Power consumption in LDPC decoder for low-power applications
#125Hierarchical channel marking in a memory system
#126Method of decoding LDPC code for producing several different decoders using parity-check matrix of LDPC code and LDPC code system including the same
#127Systems and methods for changing decoding parameters in a communication system
#128LDPC erasure decoding for flash memories
#129Memory system and data storage method
#130Adaptive ultra-low voltage memory
#131Systems and methods for selective decode algorithm modification
#132LDPC decoder with targeted symbol flipping
#133Storage device
#134Flash memory controller and data reading method
#135Memory device and method of storing data with error correction using codewords
#136Channel coding method of variable length information using block code
#137Memory controller
#138Systems and methods for operating on a storage device using a life-cycle dependent coding scheme
#139Memory controller and non-volatile storage device
#140Memory controller and operating method of memory controller
#141Memory controller and operating method of memory controller
#142Decoding method and device for concatenated code
#143BCH decoding with multiple sigma polynomial calculation algorithms
#144Device and method for error correction and protection against data corruption
#145Method and device for decoding Reed-Solomon (RS) code
#146SEMICONDUCTOR MEMORY DEVICE
#147Probabilistic multi-tier error correction in not-and (NAND) flash memory
#148Systems and methods for performing efficient decoding using a hybrid decoder
#149Dynamic buffer management in a NAND memory controller to minimize age related performance degradation due to error correction
#150Method and device for multi phase error-correction
#151System and method for restoring damaged data programmed on a flash device
#152SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING A SEMICONDUCTOR STORAGE DEVICE
#153Apparatus and method for optimizing an iterative FEC decoder
#154Flash memory device error correction code controllers and related methods and memory systems
#155Flash memory device error correction code controllers and related methods and memory systems
#156Transmitting system and method of processing digital broadcast signal in transmitting system, receiving system and method of receiving digital broadcast signal in receiving system
#157Regenerative relay system and regenerative relay apparatus
#158Power consumption in LDPC decoder for low-power applications
#159Receiver power saving via block code failure detection
#160Method and system for decoding low density parity check codes
#161Data reproducing apparatus and data reproducing method
#162Receiving apparatus, receiving method and program, and receiving system
#163Receiving apparatus, receiving method and program, and receiving system
#164Systems and methods for hard decision assisted decoding
#165Method and device for multi phase error-correction
#166Memory device with an ECC system
#167Method and apparatus for dynamically configurable multi level error correction
#168Memory device and method of storing data with error correction using codewords
#169Decoding method and error correction method of a cyclic code decoder
#170ERROR CORRECTION CIRCUIT AND METHOD THEREOF
#171Memory system and method for providing error correction
#172Channel coding method of variable length information using block code
#173Method and system for decoding a data burst in a communication system
#174Systems and methods for LDPC decoding with post processing
#175Flash memory device error correction code controllers and related methods and memory systems
#176Error correction circuit and method for reducing miscorrection probability and semiconductor memory device including the circuit
#177Systems and methods for error detection in a memory system
#178RECORDING AND/OR REPRODUCING APPARATUS AND METHOD
#179HYBRID MIN-SUM DECODING APPARATUS WITH LOW BIT RESOLUTION FOR LDPC CODE
#180System and method for data transmissin and reception
#181Method and device for multi phase error-correction
#182Regenerative relay system and regenerative relay apparatus
#183System and method for data transmission and reception
#184Extendable parity code matrix construction and utilization in a data storage device
#185Systems and methods for Nyquist error correction
#186Hybrid architecture for LDPC channel coding in data center
#187MPE-FEC system capable of selecting an FEC mode, a forward error correcting method performed in the MPE-FEC system, and an FEC mode selecting method performed in the MPE-FEC system