Early-termination of decoding convolutional codes

Electronic system with Viterbi decoder mechanism and method of operation thereof

Multimode decoder implementation method and device

Apparatus and method for generating interleaver index

Adaptive multi-core, multi-direction turbo decoder and related decoding method thereof

Systems and methods for parallel dual-mode turbo decoders

Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and turbo decoding, using carry save arithmetic

Methods and apparatus for map detection with reduced complexity

Method of selecting metrics and receiver using the same

Method and apparatus for storing survivor paths in a viterbi detector using systematic pointer exchange

Pre-decoded tail-biting convolutional code decoder and decoding method thereof

System and method for contention-free memory access

Radix-4 viterbi forward error correction decoding

Branch metrics calculation for multiple communications standards

Accessing Memory for Data Decoding

SMU architecture for turbo decoder

Apparatus and method for decoding signals

Device and method for calculating backward state metrics of a trellis

Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding

Decoding scheme for RFID reader

Path comparison unit for determining paths in a trellis that compete with a survivor path

METHOD AND APPARATUS FOR IMPROVING TRELLIS DECODING

METHOD AND APPARATUS FOR CODING RELATING TO A FORWARD LOOP

Maximum likelihood decoder and decoding method therefor

Path metric difference computation unit for computing path differences through a multiple-step trellis

Reliability unit for determining a reliability value for at least one bit decision

Methods and apparatus for processing a received signal using a multiple-step trellis and selection signals for multiple trellis paths

Methods and apparatus for map detection with reduced complexity

Methods, apparatus, and systems for determining 1T path equivalency information in an nT implementation of a viterbi decoder

Decoder using a memory for storing state metrics implementing a decoder trellis

High-speed add-compare-select (ACS) circuit

Methods, apparatus, and systems for determining 1T state metric differences in an nT implementation of a viterbi decoder

Hardware-Efficient, Low-Latency Architectures for High Throughput Viterbi Decoders

Unified stopping criteria for binary and duobinary turbo decoding in a software-defined radio system

Method and apparatus for delayed recursion decoder

VITERBI DECODING APPARATUS AND TECHNIQUES

Four-Symbol Parallel Viterbi Decoder

Memory system and method for use in trellis-based decoding

Apparatus and method for computing LLR

CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER

Method and apparatus for storing survivor paths in a Viterbi detector using input-dependent pointer exchange

Method and apparatus for storing survivor paths in a Viterbi detector using systematic pointer exchange

Single stage implementation of min*, max*, min and/or max to perform state metric calculation in SISO decoder

Decoding device and decoding method

Method and apparatus for-soft-output viterbi detection using a multiple-step trellis

Hybrid trace back apparatus and high-speed viterbi decoding system using the same

Decoder using a memory for storing state metrics implementing a decoder trellis

Maximum likelihood encoding apparatus, maximum likelihood encoding method, program and reproduction apparatus

Calculating apparatus and method for use in a maximum likelihood detector and/or decoder

Viterbi detection apparatus and method therefor

Low-latency architectures for high-throughput Viterbi decoders

Maximum likelihood detector and/or decoder

Unified serial/parallel concatenated convolutional code decoder architecture and method