222881 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Decoding methods or techniques, not specific to the particular type of coding provided for in groups - ; Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
Sub-classes:Convolutional code decoder and convolutional code decoding method
#2Iterative equalization using non-linear models in a soft-input soft-output trellis
#3Convolutional decoder and method of decoding convolutional codes
#4Sequence detector
#5Sequence detector
#6Reinforced list decoding
#7Convolutional decoder and method of decoding convolutional codes
#8Tailless convolutional codes
#9Tail biting convolutional code (TBCC) enhancement with state propagation and list decoding
#10Wireless receiver
#11Processor and method for executing wide operand multiply matrix operations
#12Iterative equalization using non-linear models in a soft-input soft-output trellis
#13Split radio architecture
#14Viterbi decoder for decoding convolutionally encoded data stream
#15Method and device for implementing Viterbi decoding
#16Processor for executing wide operand operations using a control register and a results register
#17Tail-biting convolutional decoder and decoding method
#18Technique for processing encoded information in a wireless communication network
#19Multi-channel sequential Viterbi decoder
#20Method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using burst process
#21Processor instructions to accelerate Viterbi decoding
#22Apparatus and method for processing operations in parallel using a single instruction multiple data processor
#23Apparatus and method for decoding in communication system
#24Pre-decoded tail-biting convolutional code decoder and decoding method thereof
#25Decoding tail-biting convolutional codes
#26Method for detecting the validity of downlink control information in telecommunication user equipment, decoder and baseband receiver for performing same
#27CONVOLUTIONALLY ENCODING AND DECODING MULTIPLE DATA STREAMS
#28Multi-standard viterbi processor
#29Method and system for decoding control data in GSM-based systems using inherent redundancy
#30Viterbi decoder and writing and reading method
#31Decoding method and decoding device
#32Multi-channel sequential Viterbi decoder
#33Low-latency viterbi survivor memory architecture and method using register exchange, trace-back, and trace-forward
#34High performance digital signal processing in software radios
#35Continuous parallel Viterbi decoder
#36Method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using burst process
#37Optimized Viterbi decoder and GNSS receiver
#38List Output Viterbi Deconder with Blockwise ACS and Traceback
#39Error pattern generation for trellis-based detection and/or decoding
#40Reducing equalizer error propagation with a low complexity soft output viterbi decoder
#41Decoding Apparatus and Decoding Method
#42Method and system for decoding video, voice, and speech data using redundancy
#43Select-and-insert instruction within data processing systems
#44Scalable VLIW processor for high-speed viterbi and trellis coded modulation decoding
#45Viterbi detector and information reproducing apparatus
#46Decoding scheme for RFID reader
#47Low-power predecoding based viterbi decoding
#48Reduced complexity viterbi decoding
#49METHOD AND APPARATUS FOR CODING RELATING TO A FORWARD LOOP
#50Reverse Viterbi and forward serial list Viterbi decoding for FER
#51Apparatus and method for decoding in mobile communication system
#52CONVOLUTIONAL DECODING
#53Processor for executing multiply matrix instructions requiring wide operands
#54Computer system for executing switch and table translate instructions requiring wide operands
#55Four-stage pipeline based VDSL2 Viterbi decoder
#56Processor architecture with wide operand cache
#57Programmable compute unit with internal register and bit FIFO for executing Viterbi code
#58Method for performing computations using wide operands
#59Method and apparatus for implementing decode operations in a data processor
#60Viterbi traceback initial state index initialization for partial cascade processing
#61Processor and method for executing instructions requiring wide operands for multiply matrix operations
#62Partial Response Maximum Likelihood Decoding
#63Viterbi decoder and method thereof
#64Address calculation instruction within data processing systems
#65Generic, reduced state, maximum likelihood decoder
#66Reduced state trellis decoder using programmable trellis parameters
#67Method and system for performing Viterbi decoding using a reduced trellis memory
#68System and software for performing matrix multiply extract operations
#69Forward decision aided nonlinear Viterbi detector
#70COMMUNICATIONS DIGITAL SIGNAL PROCESSOR AND DIGITAL SIGNAL PROCESSING METHOD
#71Distributed ring control circuits for Viterbi traceback
#72Programmable trellis decoder and associated methods
#73Reducing equalizer error propagation with a low complexity soft output Viterbi decoder
#74Viterbi traceback
#75Viterbi pack instruction
#76Four-Symbol Parallel Viterbi Decoder
#77MULTI-RATE VITERBI DECODER
#78Viterbi decoding circuit and wireless device
#79Memory system and method for use in trellis-based decoding
#80Data decoding apparatus and method in a communication system
#81VITERBI DECODER
#82CASCADED RADIX ARCHITECTURE FOR HIGH-SPEED VITERBI DECODER
#83Convolutional decoding
#84Viterbi decoding method and apparatus for high speed data transmissions
#85Viterbi decoding apparatus
#86Convolutionally encoding and decoding multiple data streams
#87Viterbi pretraceback for partial cascade processing
#88Apparatus and method for Viterbi decoding
#89Method for decoding tail-biting convolutional codes
#90Method and apparatus for implementing decode operations in a data processor
#91Viterbi decoder
#92Viterbi decoder architecture for use in software-defined radio systems
#93Decoder with M-AT-A-Time Traceback
#94Viterbi decoder for executing trace-back work in parallel and decoding method
#95Error correction decoder
#96Scalable traceback technique for channel decoder
#97Method and system for decoding control data in GSM-based systems using inherent redundancy
#98Method and system for decoding single antenna interference cancellation (SAIC) and redundancy processing adaptation using burst process
#99Apparatus and method for decoding and trace back of convolution codes using the viterbi decoding algorithm
#100Distributed ring control circuits for Viterbi traceback
#101Decoding circuit and decoding method for a Viterbi decoder
#102Method and system for decoding video, voice, and speech data using redundancy
#103Method of and apparatus for implementing a reconfigurable trellis-type decoding
#104Multi-rate viterbi decoder
#105Method of and apparatus for implementing fast orthogonal transforms of variable size
#106Memory management algorithm for trellis decoders
#107Viterbi decoder with survivor bits stored to support look-ahead addressing
#108Communications digital signal processor and digital signal processing method
#109Method for determining signal quality of simultaneously received multiple channels of data
#110Unified viterbi/turbo decoder for mobile communication systems
#111Trellis decoder and method of decoding
#112HDTV trellis decoder architecture
#113Method and system for branch metric calculation in a viterbi decoder
#114Reconfigurable Viterbi/turbo decoder
#115Reduced complexity decoding for trellis coded modulation
#116Parallel backtracking in Viterbi decoder
#117Sequence detection
#118Fixed-point detector pruning for constrained codes
#119Error event processing methods and systems