222923 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Purpose and implementation aspects; Reduction of hardware complexity or efficient processing Memory efficient implementations
DECODING METHOD AND STORAGE DEVICE
#2ERROR DETECTION
#3METHODS AND APPARATUS FOR COMPACTLY DESCRIBING LIFTED LOW-DENSITY PARITY-CHECK (LDPC) CODES
#4APPARATUSES AND METHODS FOR ECC PARITY BIT REDUCTION
#5ERROR DETECTION
#6Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
#7High performance, flexible, and compact low-density parity-check (LDPC) code
#8Memory system
#9Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
#10Tile based interleaving and de-interleaving for digital signal processing
#11Memory system
#12Polar decoder with LLR-domain computation of f-function and g-function
#13High performance, flexible, and compact low-density parity-check (LDPC) code
#14Tile based interleaving and de-interleaving for digital signal processing
#15Low density parity check encoder having length of 16200 and code rate of 4/15, and low density parity check encoding method using the same
#16Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
#17Memory system
#18High performance, flexible, and compact low-density parity-check (LDPC) code
#19Tile based interleaving and de-interleaving for digital signal processing
#20High performance, flexible, and compact low-density parity-check (LDPC) code
#21Techniques for fast IO and low memory consumption while using erasure codes
#22Memory system
#23Communication control apparatus, radio communication apparatus, communication control method, and radio communication method
#24Non-volatile Storage Systems With Application-Aware Error-Correcting Codes
#25Parallel pipeline logic circuit for generating CRC values utilizing lookup table
#26Low-power low density parity check decoding
#27Sequential decoding with stack reordering
#28Reduced-stage polar decoding
#29Method and system for LDPC decoding
#30High performance, flexible, and compact low-density parity-check (LDPC) code
#31Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes
#32Systems and methods for latency based data recycling in a solid state memory system
#33Fully parallel turbo decoding
#34Protecting in-memory immutable objects through hybrid hardware/software-based memory fault tolerance
#35In-memory data storage with transparent compression
#36Low density parity check encoder having length of 16200 and code rate of 4/15, and low density parity check encoding method using the same
#37Validation bits and offsets to represent logical pages split between data containers
#38Validation bits and offsets to represent logical pages split between data containers
#39Low-power low density parity check decoding
#40Validation bits and offsets to represent logical pages split between data containers
#41Systems and methods of memory bit flip identification for debugging and power management
#42Systems and methods for latency based data recycling in a solid state memory system
#43Reduced complexity non-binary LDPC decoding algorithm
#44Low-power low density parity check decoding
#45Turbo decoder with a low-power input format and associated method
#46Reduced memory iterative baseband processing
#47Generating molecular encoding information for data storage
#48Low density parity check circuit
#49Forward error correction with configurable latency
#50Soft metrics compressing method
#51Dynamic data density ECC
#52EFFICIENT IMPLEMENTATION TO PERFORM ITERATIVE DECODING WITH LARGE ITERATION COUNTS
#53System and method for multi standard programmable LDPC decoder
#54Reduced complexity non-binary LDPC decoding algorithm
#55Systems and methods for latency based data recycling in a solid state memory system
#56Syndrome tables for decoding turbo-product codes
#57Memory efficient implementation of LDPC decoder
#58Parallel low-density parity check (LDPC) accumulation
#59Method and device for transmitting data
#60Memory architecture for layered low-density parity-check decoder
#61Low-power low density parity check decoding
#62Forward error correction with configurable latency
#63LEH memory module architecture design in the multi-level LDPC coded iterative system
#64Tile based interleaving and de-interleaving for digital signal processing
#65Conserving computing resources during error correction
#66Systems and methods for parallel dual-mode turbo decoders
#67Reduced complexity non-binary LDPC decoding algorithm
#68High throughput decoder architecture for low-density parity-check convolutional codes
#69Method and apparatus for soft information transfer between constituent processor circuits in a soft-value processing apparatus
#70Error detection and correction for external DRAM
#71Channel decoding method and decoder for tail-biting codes
#72Low density parity check code decoding system and method
#73Memory-efficient LDPC decoding
#74Error correcting code decoding device, decoding method, and mobile station apparatus
#75Techniques for rate matching and de-rate matching
#76Memory controller, semiconductor memory apparatus and decoding method
#77Overlapping sub-matrix based LDPC (low density parity check) decoder
#78Method for controlling a basic parity node of a non-binary LDPC code decoder, and corresponding basic parity node processor
#79Satellite communication system utilizing low density parity check codes
#80Memory efficient implementation of LDPC decoder
#81COMMUNICATION APPARATUS, COMMUNICATION METHOD AND STORAGE MEDIUM FOR FLEXIBLE ERROR CORRECTION
#82Memory device on the fly CRC mode
#83Low complexity decoding algorithm for tail-biting convolutional codes
#84Forward error correction with configurable latency
#85Techniques for successive refinement of metrics stored for HARQ combining
#86Increasing hybrid automatic repeat request (HARQ) throughput
#87Data rearrangement for decoder
#88Accessing Memory for Data Decoding
#89Reliability support in memory systems without error correcting code support
#90Pipeline architecture for maximum a posteriori (MAP) decoders
#91Decoding device, data communication apparatus having the decoder device, and data memory
#92NODE INFORMATION STORAGE METHOD AND SYSTEM FOR A LOW-DENSITY PARITY-CHECK DECODER
#93Distributed processing LDPC (low density parity check) decoder
#94Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same
#95Satellite communication system utilizing low density parity check codes
#96Apparatus and method for generating a parity check matrix in a communication system using linear block codes, and a transmission/reception apparatus and method using the same
#97Error detection and correction for external DRAM
#98Recursive realization of polynomial permutation interleaving
#99Systematic encoder with arbitrary parity positions
#100Method and apparatus for elementary updating a check node during decoding of a block encoded with a non-binary LDPC code
#101Decoding method for tail-biting convolutional codes using a search depth viterbi algorithm
#102Nonvolatile random access memory and nonvolatile memory system
#103Error correcting apparatus, method of controlling memory of error correcting apparatus, and optical disc recording/reproducing apparatus
#104Memory-efficient storage method: a fast BJCR based decoder implementation scheme
#105Soft output viterbi decoder architecture
#106List Output Viterbi Deconder with Blockwise ACS and Traceback
#107Decoding device, data storage device, data communication system, and decoding method
#108CHANNEL ENCODING
#109Decoding Method and System for Low-Density Parity Check Code
#110Decoding device and receiving device
#111Overlapping sub-matrix based LDPC (low density parity check) decoder
#112Scalable decoder architecture for low density parity check codes
#113Method and apparatus for deinterleaving in a digital communication system
#114Arithmetic circuit for concatenated codes and address control method
#115Address generation for multiple access of memory
#116Reduced complexity LDPC decoder
#117Parallel concatenated code with soft-in soft-out interactive turbo decoder
#118Memory Access in Low-Density Parity Check Decoders
#119TURBO DECODER, BASE STATION AND DECODING METHOD
#120LDPC encoder and decoder and LDPC encoding and decoding methods
#121Method of de-interleaving interleaved data samples sequences, and associated system
#122Turbo decoding apparatus and method
#123Decoding apparatus and decoding method
#124Grouping bits interleaving apparatus and method thereof
#125Memory depth optimization in communications systems with ensemble PHY layer requirements
#126Apparatus and method for error correction in mobile wireless applications incorporating erasure table data
#127Method and apparatus for turbo code decoding
#128METHOD AND DEVICE FOR DECODING LOW DENSITY PARITY CHECK CODE
#129Method and application for generating interleaver or de-interleaver
#130State metrics memory reduction in a turbo decoder implementation
#131APPARATUS AND METHOD FOR BLOCK INTERLEAVING IN MOBILE COMMUNICATION SYSTEM
#132Method and apparatus for implementing decode operations in a data processor
#133Distributed processing LDPC (low density parity check) decoder
#134Efficient implementation to perform iterative decoding with large iteration counts
#135Compact MPE-FEC erasure location cache memory for DVB-H receiver
#136Memory-efficient LDPC decoder and method
#137Addressing strategy for Viterbi metric computation
#138Raid system and data recovery apparatus using galois field
#139Coding device, decoding device, transmitter and receiver
#140Data processing systems and methods for processing digital data with low density parity check matrix
#141Turbo decoding apparatus
#142Overlapping sub-matrix based LDPC (low density parity check) decoder
#143Distributed ring control circuits for Viterbi traceback
#144Methods and apparatus for improved error and erasure correction in a Reed-Solomon date channel
#145Method and device for decoding blocks encoded with an LDPC code
#146Parallel concatenated code with soft-in soft-out interactive turbo decoder
#147RECEIVER ARCHITECTURE HAVING A LDPC DECODER WITH AN IMPROVED LLR UPDATE METHOD FOR MEMORY REDUCTION
#148Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
#149Remainder calculating apparatus for cyclic redundancy check
#150Device and method for receiving digital signal transmitted using OFDM method
#151Decoding method for tail-biting convolutional codes using a search depth viterbi algorithm
#152Viterbi pack instruction
#153Methods and apparatuses for generating parity symbols for data block
#154Decoding device, control method, and program
#155MULTI-RATE VITERBI DECODER
#156LOW COMPLEXITY CHANNEL DECODERS
#157Memory system and method for use in trellis-based decoding
#158Decompressing method and device for matrices
#159Pipeline architecture for maximum a posteriori (MAP) decoders
#160Decoding of multiple data streams encoded using a block coding algorithm
#161Iterative stripewise trellis-based symbol detection method and device for multi-dimensional recording systems
#162In-place transformations with applications to encoding and decoding various classes of codes
#163Buffering of data from a data stream having error correction elements
#164Method and apparatus for calibrating data-dependent noise prediction
#165Parallel concatenated code with soft-in-soft-out interactive turbo decoder
#166Apparatus and method for Viterbi decoding
#167Methods and apparatus for decoding LDPC codes
#168Method and apparatus for implementing decode operations in a data processor
#169Decomposer for parallel turbo decoding, process and integrated circuit
#170Iterative stripwise trellis-based symbol detection method and device for multi-dimensional recording systems
#171Turbo decoding apparatus and interleave-deinterleave apparatus
#172Puncturing/depuncturing using compressed differential puncturing pattern
#173Distributed ring control circuits for Viterbi traceback
#174Efficient backward recursion for computing posterior probabilities
#175Multi-rate viterbi decoder
#176Pipeline architecture for maximum a posteriori (MAP) decoders
#177Methods and apparatus for decoding LDPC codes
#178Add-compare-select-offset device and method in a decoder
#179Efficient design to implement LDPC (Low Density Parity Check) decoder
#180Method and apparatus for performing low-density parity-check (LDPC) code operations using a multi-level permutation
#181Memory management algorithm for trellis decoders
#182Decoding apparatus, decoding method, and program to decode low density parity check codes
#183Method and apparatus for calibrating data-dependent noise prediction
#184Method and arrangement for enhancing search through trellis
#185Turbo-code decoding using variably set learning interval and sliding window
#186Error control apparatus
#187Method for determining signal quality of simultaneously received multiple channels of data
#188Decoding apparatus, decoding method, data-receiving apparatus and data-receiving method
#189Methods and apparatus for coding and decoding data using Reed-Solomon codes
#190Method of de-interleaving interleaved data samples sequences, and associated system
#191Data compression with incremental redundancy
#192LDPC decoder, corresponding method, system and computer program
#193Method to efficiently generate the row and column index for half rate interleaver in GSM
#194Non-binary viterbi data processing system and method
#195Configurable architecture and its implementation of viterbi decorder
#196Satellite communication system utilizing low density parity check codes
#197Signal processing method and signal processing circuit
#198Parallel concatenated code with soft-in soft-out interactive turbo decoder
#199Parallel concatenated code with soft-in soft-out interactive turbo decoder
#200Parallel concatenated code with soft-in soft-out interactive turbo decoder
#201Method and system for generating parallel decodable low density parity check (LDPC) codes