222925 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Purpose and implementation aspects; Flexibility, adaptability, parametrability and configurability of the implementation Support of multiple decoding rules, e.g. combined MAP and Viterbi decoding
KALMAN FILTER BASED PHASE-LOCKED LOOP WITH RE-ENCODING BASED PHASE DETECTOR
#2PMD-TO-TC-MAC INTERFACE WITH 2-STAGE FEC PROTECTION
#3CONCATENATED ERROR CORRECTING CODES
#4PMD-TO-TC-MAC INTERFACE WITH 2-STAGE FEC PROTECTION
#5Scaled bit flip thresholds across columns for irregular low density parity check decoding
#6Concatenated error correcting codes
#7PMD-to-TC-MAC interface with 2-stage FEC protection
#8Concatenated error correcting codes
#9CHANNEL CODING METHOD, CHANNEL CODING APPARATUS, CHIP SYSTEM, AND STORAGE MEDIUM
#10Low power error correcting code (ECC) system
#11Configurable ECC decoder
#12ECC decoder with selective component disabling based on decoding message resolution
#13Adjusted min-sum decoder
#14Method and system for operating a communication circuit configurable to support one or more data rates
#15Systems and methods for locating and correcting decoder mis-corrections
#16Systems and methods for back step data decoding
#17Using a soft decoder with hard data
#18Technique for optimization and re-use of hardware in the implementation of instructions used in Viterbi and turbo decoding, using carry save arithmetic
#19Turbo coding for upstream and downstream transmission over a channel
#20End-to end data protection supporting multiple CRC algorithms
#21END-TO-END DATA PROTECTION SUPPORTING MULTIPLE CRC ALGORITHMS
#22Architecture and control of reed-solomon error-correction decoding
#23Processor for processing digital data with butterfly operator for the execution of an FFT/IFFT and telecommunication device
#24System, method and apparatus for tail biting convolutional code decoding
#25Soft output Viterbi algorithm method and decoder
#26Architecture and control of Reed-Solomon error-correction decoding
#27Branch metrics calculation for multiple communications standards
#28Configurable coding system and method of multiple ECCS
#29Error correction decoding by trial and error
#30Turbo coding for upstream and downstream transmission in cable systems
#31System to improve memory failure management and associated methods
#32System for error control coding for memories of different types and associated methods
#33Unified decoder for convolutional, turbo, and LDPC codes
#34Architecture and control of reed-solomon error identification and evaluation
#35Architecture and control of reed-solomon error-correction decoding
#36Architecture and control of Reed-Solomon error-correction decoding
#37Architecture and control of Reed-Solomon list decoding
#38Denoising and error correction for finite input, general output channel
#39Multimode decoder
#40Universal error control coding system for digital communication and data storage systems
#41Programmable trellis decoder and associated methods
#42Method and system for increasing decoder throughput
#43Universal error control coding scheme for digital communication and data storage systems
#44Error correction decoding by trial and error
#45Apparatus and method for receiving signal in a communication system using a low density parity check code
#46Reconfigurable bit-manipulation node
#47Reconfigurable bit-manipulation node
#48Method for iterative decoding in a digital system and apparatus implementing the method
#49Techniques for reconfigurable decoder for a wireless system
#50Adaptive Viterbi decoder for a wireless data network receiver
#51Decoder, decoding method, and disk playback device
#52Method of and apparatus for implementing fast orthogonal transforms of variable size
#53Apparatus and methods for forward error correction decoding
#54Unified serial/parallel concatenated convolutional code decoder architecture and method