222928 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Purpose and implementation aspects; Flexibility, adaptability, parametrability and configurability of the implementation Support of multiple transmission or communication standards
Error rate measuring apparatus and uncorrectable codeword search method
#2Broadcast system and method for error correction using separately received redundant data and broadcast data
#3Transmitting apparatus and interleaving method thereof
#4Broadcast system and method for error correction using separately received redundant data and broadcast data
#5Fully parallel turbo decoding
#6Transmitting apparatus and interleaving method thereof
#7Apparatus and method for sending and receiving broadcast signals
#8Multimode decoder implementation method and device
#9Self-configurable device for interleaving/deinterleaving data frames
#10Broadcast system and method for error correction using redundant data
#11Using CRC residual value to distinguish a recipient of a data packet in a communication system
#12System and method for multi standard programmable LDPC decoder
#13Method and system for operating a communication circuit configurable to support one or more data rates
#14Combination A/53 and A/153 receiver using a HIHO viterbi decoder
#15Encoding/decoding processor and wireless communication apparatus
#16Apparatus and method for a dual mode standard and layered belief propagation LDPC decoder
#17Encoder and encoding method providing incremental redundancy
#18ERROR CORRECTION METHOD AND DEVICE
#19Interleaver with parallel address queue arbitration dependent on which queues are empty
#20Radix-4 viterbi forward error correction decoding
#21Reconfigurable encoding per multiple communications standards
#22Branch metrics calculation for multiple communications standards
#23Multi-standard viterbi processor
#24Reconfigurable interleaver having reconfigurable counters
#25Reducing power consumption in an iterative decoder
#26Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards
#27Cyclic shift device, cyclic shift method, LDPC decoding device, television receiver, and reception system
#28Method and apparatus for parallel processing turbo decoder
#29Apparatus and method for generating a parity check matrix in a communication system using linear block codes, and a transmission/reception apparatus and method using the same
#30RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS
#31Contention-free parallel processing multimode LDPC decoder
#32Multi-mode forward error correction
#33Method and apparatus for parallel processing multimode LDPC decoder
#34Method and apparatus for software-defined radio LDPC decoder
#35Methods and apparatus for programmable decoding of a plurality of code types
#36Digital broadcasting transmitter, turbo stream processing method thereof, and digital broadcasting system having the same
#37Digital broadcasting transmitter, turbo stream processing method thereof, and digital broadcasting system having the same
#38DIGITAL BROADCASTING TRANSMITTER, TURBO STREAM PROCESSING METHOD THEREOF, AND DIGITAL BROADCASTING SYSTEM HAVING THE SAME
#39Digital broadcasting transmitter, turbo stream processing method thereof, and digital broadcasting system having the same
#40Digital broadcasting transmitter, turbo stream processing method thereof, and digital broadcasting system having the same
#41PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
#42PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
#43PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
#44PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
#45ELECTRONIC DATA SHIFT DEVICE, IN PARTICULAR FOR CODING/DECODING WITH AN LDPC CODE
#46PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
#47PROCESSING WIRELESS AND BROADBAND SIGNALS USING RESOURCE SHARING
#48Method and apparatus for switching data in communication system
#49Generic, reduced state, maximum likelihood decoder
#50Method and system for performing Viterbi decoding using a reduced trellis memory
#51Method and system for increasing decoder throughput
#52Interleaver interface for a software-defined radio system
#53Unified stopping criteria for binary and duobinary turbo decoding in a software-defined radio system
#54Turbo decoder input reordering
#55Viterbi decoding circuit and wireless device
#56Equalization techniques using viterbi algorithms in software-defined radio systems
#57Reconfigurable bit-manipulation node
#58Reconfigurable bit-manipulation node
#59Digital broadcasting transmitter, turbo stream processing method thereof, and digital broadcasting system having the same
#60Multi-standard turbo interleaver using tables
#61Techniques for reconfigurable decoder for a wireless system
#62Pre-emptive interleaver address generator for turbo decoders
#63Viterbi decoder architecture for use in software-defined radio systems
#64Signal processing circuit
#65Unified interleaver/de-interleaver