DECODER SCHEME CAPABLE OF REDUCING FREQUENCY OF MEMORY READING AND WRITING DURING ITERATIVE DECODING PROCEDURE

COMMUNICATON DEVICE WITH LOW DENSITY PARITY CHECK ROTATOR, AND METHOD THEREFOR

Codeword rotation for zone grouping of media codewords

Tiered error correction code (ECC) operations in memory

Codeword rotation for zone grouping of media codewords

Decoder for low-density parity-check codes

Nonvolatile memory device and read and copy-back methods thereof

Adaptive read retry optimization

Tiered error correction code (ECC) operations in memory

Accommodating variable page sizes in solid-state drives using customized error correction

LDPC performance improvement using SBE-LBD decoding method and LBD collision reduction

Decoding method and decoding system for a parity check code

Decoder for low-density parity-check codes

Permutation network designing method, and permutation circuit of QC-LDPC decoder

Memory device error check and scrub mode and error transparency

Multi-phase dispersed storage write process

Error correcting code testing

Determining codebooks for different memory areas of a storage device

Use of multiple codebooks for programming data in different memory areas of a storage device

Bit-order modification for different memory areas of a storage device

Tiered error correction code (ECC) operations in memory

Dispersed storage write process with lock/persist

ECC and read adjustment based on dynamic memory error model estimation

Scheduling method of a parity check matrix and an LDPC decoder for performing scheduling of a parity check matrix

Information processing device and host device

Storage device that inverts bits of data written into a nonvolatile memory thereof

LDPC performance improvement using SBE-LBD decoding method and LBD collision reduction

Lossless pixel compression for random video memory access

Semiconductor devices and semiconductor systems

Nonvolatile memory device and read and copy-back methods thereof

HARDWARE-ASSISTED PROTECTION FOR SYNCHRONOUS INPUT/OUTPUT

Memory system and operating method thereof

SYSTEM AND METHOD FOR REGENERATING CODES FOR A DISTRIBUTED STORAGE SYSTEM

Encoding method, decoding method, encoding device and decoding device for structured LDPC

SECURE MESSAGE DELIVERY IN A DISPERSED STORAGE NETWORK

Assigning redundancy in encoding data onto crossbar memory arrays

Memory-aware matrix factorization

Memory-aware matrix factorization

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

Semiconductor device

Self-addressing memory

MEMORY SYSTEM INCLUDING ERROR CORRECTOR AND OPERATING METHOD THEREOF

Memory device on-die error checking and correcting code

Memory device error check and scrub mode and error transparency

Memory device check bit read mode

Low density parity check decoding method performing on general graphic processing unit and decoding apparatus

Memory-aware matrix factorization

Turbo decoder with a low-power input format and associated method

Memory corruption detection

Configuring circuitry with memory access constraints for a program

Memory system configured to avoid memory access hazards for LDPC decoding

Self-addressing memory

Decoder and decoding method thereof for min-sum algorithm low density parity-check code

Low density parity-check code decoder and decoding method thereof

Codes of length tn invariant under rotations of order n

Decoding method, memory storage device and memory controlling circuit unit

Method of programming memory device and method of reading data of memory device including the same

Memory system and method of controlling memory system

Dynamic data density ECC

Decoder for low-density parity-check codes

SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA

Low density parity check (LDPC) encoding and decoding for small terminal applications

Memory architecture for layered low-density parity-check decoder

Programming a non-volatile memory (NVM) system having error correction code (ECC)

System and method for check-node unit message processing

Error correction code circuit and memory device including the same

Multicore type error correction processing system and error correction processing apparatus

Multi-processing architecture for an LTE turbo decoder (TD)

Error detection and correction for external DRAM

Nonvolatile memory, memory controller, nonvolatile memory accessing method, and program

Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix

System and method for contention-free memory access

Error correction code decoding device

Communications system employing local and global interleaving/de-interleaving

Accessing memory during parallel turbo decoding

Data rearrangement for decoder

Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave

Accessing Memory for Data Decoding

Reliability support in memory systems without error correcting code support

Multi-code LDPC (low density parity check) decoder

Apparatus and method for layered decoding in a communication system using low-density parity-check codes

Method and apparatus for parallel de-interleaving of LTE interleaved data

Decoding device, data communication apparatus having the decoder device, and data memory

Method and apparatus for encoding and decoding data

N-way parallel turbo decoder architecture

Method for arranging memories of low-complexity LDPC decoder and low-complexity LDPC decoder using the same

Turbo decoding device and communication device

Error detection and correction for external DRAM

Data handling system comprising memory banks and data rearrangement

Reduced contention storage for channel coding

Fast encoding and decoding methods and related devices

Contention free parallel access system and a method for contention free parallel access to a group of memory banks

LDPC decoder and method for LDPC decoding based on layered algorithm applied to parity check matrix

Shuffled LDPC decoding

Systems and methods for error correction and decoding on multi-level physical media

METHOD FOR DECODING LDPC CODE AND THE CIRCUIT THEREOF

METHOD AND SYSTEM FOR PROVIDING LOW DENSITY PARITY CHECK (LDPC) CODING FOR SCRAMBLED CODED MULTIPLE ACCESS (SCMA)

Address generation for multiple access of memory

Memory architecture for high throughput RS decoding for MediaFLO receivers

Memory Access in Low-Density Parity Check Decoders

Turbo LDPC decoding

De-interleaving mechanism involving a multi-banked LLR buffer

Architecture to handle concurrent multiple channels

Decoding apparatus and decoding method

Apparatus of multi-stage network for iterative decoding and method thereof

VITERBI DECODING APPARATUS AND METHOD

Method, apparatus, computer program product and device providing semi-parallel low density parity check decoding using a block structured parity check matrix

Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding

Apparatus and method for decoding low density parity check coded signals

Multi-code LDPC (low density parity check) decoder

Multiple access for parallel turbo decoder

Decoding apparatus

Turbo LDPC decoding

Adaptable channel compensation for reliable communication over fading communication links

Turbo decoder

Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave

Quadratic polynomial permutation (QPP) interleaver providing hardware savings and flexible granularity adaptable to any possible turbo code block size

Method and apparatus for encoding and decoding data

Turbo decoder and turbo decoding method

Error correction code decoding device

Method and apparatus for encoding and decoding data

Apparatus and method for decoding using channel code

Method and device for decoding blocks encoded with an LDPC code

Methods and apparatus for low-density parity check decoding using hardware-sharing and serial sum-product architecture

Method and device for layered decoding of a succession of blocks encoded with an LDPC code

High spread highly randomized generatable interleavers

LDPC decoding apparatus and method based on node memory

Decoding device, control method, and program

Implementation of LDPC (low density parity check) decoder by sweeping through sub-matrices

Sub-matrix-based implementation of LDPC (Low Density Parity Check) decoder

Decoding of multiple data streams encoded using a block coding algorithm

Block processing in a block decoding device

Deinterleaver and dual-viterbi decoder architecture

Clash-free irregular-repeat-accumulate code

Techniques for reconfigurable decoder for a wireless system

Convolutional interleaver/de-interleaver

Methods and apparatus for decoding LDPC codes

Decomposer for parallel turbo decoding, process and integrated circuit

Adaptable channel compensation for reliable communication over fading communication links

Method and device for decoding DVB-S2 LDPC encoded codewords

LDPC decoder for DVB-S2 decoding

System and method for multi-mode multi-state path metric addressing

Semiconductor memory device

Memory device for use in high-speed block pipelined reed-solomon decoder, method of accessing the memory device, and reed-solomon decoder having the memory device

Block de-interleaving system

LDPC decoder

Methods and apparatus for decoding LDPC codes

Decoding method, decoding apparatus, and program to decode low density parity check codes

Apparatus and method for decoding low density parity check codes

Decoding apparatus, decoding method, and program to decode low density parity check codes

Electronic device for reducing interleaving write access conflicts in optimized concurrent interleaving architecture for high throughput turbo decoding

Method and device for handling write access conflicts in interleaving for high throughput turbo-decoding

LDPC decoder, corresponding method, system and computer program

High spread highly randomized generatable interleavers

Interleaver and device for decoding digital signals comprising such an interleaver

Polar codes for error correction in non-volatile memory devices

Extendable parity code matrix construction and utilization in a data storage device

Adaptive read retry optimization

Method for using write intents in a distributed storage network

Writing copies of objects in enterprise object storage systems