222946 ⎘
Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes; Purpose and implementation aspects Implementation on processors, e.g. DSPs, or software implementations
ACCELERATOR DEVICE AND METHOD OF CONTROLLING ACCELERATOR DEVICE
#2Optimized implementation of (DE−)interleaving and rate (DE−)matching for 3GPP new radio
#3Optimized implementation of (de-)interleaving and rate (de-)matching for 3GPP new radio
#4Storage system and method for interleaving data for enhanced quality of service
#5Verifying the correctness of a deflate compression accelerator
#6Verifying the correctness of a deflate compression accelerator
#7Verifying the correctness of a deflate compression accelerator
#8Program flow monitoring for deterministic firmware functions
#9Flexible error correction
#10Program flow monitoring for deterministic firmware functions
#11Method for layered storage of enterprise data
#12Self-addressing memory
#13Low power low-density parity-check decoding
#14Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction
#15Configuring circuitry with memory access constraints for a program
#16Memory system configured to avoid memory access hazards for LDPC decoding
#17Self-addressing memory
#18Self-configurable device for interleaving/deinterleaving data frames
#19Parallel processing of overlapping subsequences to generate soft estimates
#20Parallel execution of trellis-based methods using overlapping sub-sequences
#21Recursion unit scheduling
#22Multicore type error correction processing system and error correction processing apparatus
#23Systems and methods for non-binary decoding biasing control
#24Processor instructions to accelerate Viterbi decoding
#25Low latency SIMD architecture for iterative decoders
#26Data input and output method of NAND flash memory and embedded system using the same
#27System and method for Viterbi decoding using application specific extensions
#28Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction
#29Parallel execution of trellis-based methods
#30Programmable cyclic redundancy check CRC unit
#31Receiver equipped with a trellis viterbi decoder
#32Optimized Viterbi decoder and GNSS receiver
#33ASIP architecture for executing at least two decoding methods
#34MAXIMUM LIKELIHOOD DECODER AND INFORMATION REPRODUCTION APPARATUS
#35Contention-free parallel processing multimode LDPC decoder
#36Method and apparatus for parallel processing multimode LDPC decoder
#37Method and apparatus for software-defined radio LDPC decoder
#38Methods and apparatus for programmable decoding of a plurality of code types
#39LDPC codes and stochastic decoding for optical transmission
#40Methods and apparatus for reduced complexity soft-output viterbi detection
#41Rate matching device and method for a date communication system
#42Efficient chien search method in reed-solomon decoding, and machine-readable recording medium including instructions for executing the method
#43Method for efficiently calculating syndromes in reed-solomon decoding, and machine-readable storage medium storing instructions for executing the method
#44Vector Crc Computatuion on Dsp
#45Decoder for low-density parity-check convolutional codes
#46Rate matching device and method for a data communication system
#47Apparatus and method using reduced memory for channel decoding in a software-defined radio system
#48COMMUNICATIONS DIGITAL SIGNAL PROCESSOR AND DIGITAL SIGNAL PROCESSING METHOD
#49Viterbi traceback
#50Four-Symbol Parallel Viterbi Decoder
#51CONFIGURABLE INTERFACE FOR CONNECTING VARIOUS CHIPSETS FOR WIRELESS COMMUNICATION TO A PROGRAMMABLE (MULTI-)PROCESSOR
#52Equalization techniques using viterbi algorithms in software-defined radio systems
#53Reconfigurable bit-manipulation node
#54Reconfigurable bit-manipulation node
#55Error correction device, error correction program and error correction method
#56In-place transformations with applications to encoding and decoding various classes of codes
#57Viterbi decoder architecture for use in software-defined radio systems
#58System and method for multi-mode multi-state path metric addressing
#59Even-load software Reed-Solomon decoder
#60Method and apparatus for encoding and decoding data
#61Communications digital signal processor and digital signal processing method
#62Methods and apparatus for coding and decoding data using Reed-Solomon codes
#63Methods and systems for Viterbi decoding
#64Reduced complexity decoding for trellis coded modulation