ClassID:

223298

H04B1/0046 - CPC Classification

Classification description:

Details of transmission systems, not covered by a single one of groups - ; Details of transmission systems not characterised by the medium used for transmission; Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage Decimation, i.e. data rate reduction techniques

Recent Application in this class:
#1
20240146402
2024-05-02

Integrated mixed-signal ASIC with ADC, DAC, and DSP

#2
20220271830
2022-08-25

Integrated mixed-signal ASIC with ADC, DAC, and DSP

#3
20220263529
2022-08-18

Maximizing efficiency of communication systems with self-interference cancellation subsystems

#4
20210263066
2021-08-26

Method for offset calibration of a yaw rate sensor signal of a yaw rate sensor, system and computer program

#5
20210234609
2021-07-29

Integrated mixed-signal ASIC with ADC, DAC, and DSP

#6
20210211144
2021-07-08

Efficient polyphase architecture for interpolator and decimator

#7
20210021289
2021-01-21

Variable-rate decoder-based wireless receiver

#8
20200274558
2020-08-27

Method for determining MIMO detection matrix of scheduled UE

#9
20200220613
2020-07-09

Integrated mixed-signal RF transceiver with ADC, DAC, and DSP and high-bandwidth coherent recombination

#10
20200052726
2020-02-13

Efficient polyphase architecture for interpolator and decimator

#11
20180367169
2018-12-20

Transformation based filter for interpolation or decimation

#12
20180254785
2018-09-06

Efficient polyphase architecture for interpolator and decimator

#13
20180248575
2018-08-30

Wideband receiver architecture tolerant to in-band interference

#14
20180191383
2018-07-05

Transformation based filter for interpolation or decimation

#15
20180115329
2018-04-26

Efficient polyphase architecture for interpolator and decimator

#16
20170063446
2017-03-02

Integrated mixed-signal ASIC with DAC and DSP

#17
20170054492
2017-02-23

Integrated mixed-signal ASIC with ADC and DSP

#18
20160100455
2016-04-07

Multi-carrier base station receiver

#19
20130279556
2013-10-24

Receiver with variable gain elements and automatic gain control to maintain a positive signal to noise ratio margin

#20
20130260707
2013-10-03

Controlling filter bandwidth based on blocking signals

#21
20130202067
2013-08-08

Heterodyne receiver structure, multi chip module, multi integrated circuit module, and method for processing a radio frequency signal

#22
20130163512
2013-06-27

Multi-band crest factor reduction

#23
20130070818
2013-03-21

Receiver

#24
20130070815
2013-03-21

ADC clock selection based on determined maximum conversion rate

#25
20130016619
2013-01-17

System and method for controlling current to certain components of a wireless communication device

#26
20090221249
2009-09-03

Method and arrangement for signal processing in a receiver that can be tuned to different carriers