Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit of a memory controller

TIMESLOT MAPPING AND/OR AGGREGATION ELEMENT FOR DIGITAL RADIO FREQUENCY TRANSPORT ARCHITECTURE

MULTIPLEXER AND SERIALIZER INCLUDING THE SAME

PWM waveform generation device and method thereof

High-speed transmitter including a multiplexer using multi-phase clocks

Overlapped multiplexing modulation method, apparatus and system

Timeslot mapping and/or aggregation element for digital radio frequency transport architecture

Systems and methods for multiple network access by mobile computing devices

METHOD AND APPARATUS FOR CIRCUIT EMULATION WITH INTEGRATED NETWORK DIAGNOSTICS AND REDUCED FORM FACTOR IN LARGE PUBLIC COMMUNICATION NETWORKS

Control method, transmission apparatus, and recording medium comparing versions of circuit data and copying to match circuit data of first and second interfaces

Low-power CML-less transmitter architecture

Encoding and decoding method for short-range communication using an acoustic communication channel

Method and system to enhance management channels

Scalable interconnect modules with flexible channel bonding

Systems and methods for programmatically filtering frequency signals

DOWNSTREAM ADAPTIVE MODULATION IN BROADBAND COMMUNICATIONS SYSTEMS

Method and apparatus for multiplexing ethernet channels

Method and apparatus for circuit emulation with integrated network diagnostics and reduced form factor in large public communication networks

Symmetrical clock distribution in multi-stage high speed data conversion circuits

Transport of multiple asynchronous data streams using higher order modulation

Network element of a communication network

Multi-channel sample rate converter

Scalable interconnect modules with flexible channel bonding

INTERFACE CIRCUIT

Method and apparatus for signal formation with guaranteed consistent overhead insertion

Symmetrical clock distribution in multi-stage high speed data conversion circuits

Encoder, decoder, encoding method, and decoding method

Downstream adaptive modulation in broadband communications system

Multiple high-speed bit stream interface circuit

Multiple E-carrier transport over DSL

System and method for multiplexing fractional TDM frames

Transmission system and transmission method

Conditioning circuit that spectrally shapes a serviced bit stream

Symmetrical clock distribution in multi-stage high speed data conversion circuits

TRANSCEIVER SYSTEM AND METHOD SUPPORTING VARIABLE RATES AND MULTIPLE PROTOCOLS

Bit stream conditioning circuit having adjustable input sensitivity

Module for Network Interface Card

Multiple high-speed bit stream interface circuit

Low-speed DLL employing a digital phase interpolator based upon a high-speed clock

Downstream adaptive modulation in broadband communications system

Configurable logic circuit arrangement

Low-speed DLL employing a digital phase interpolator based upon a high-speed clock

Transceiver, optical transmitter, port-based switching method, program, and storage medium

Data de-skew method and system

Transmitting interleaved multiple data flows

Time multiplexed SONET line processing

System and method for tuning output drivers using voltage controlled oscillator capacitor settings

Field reconfigurable line cards for an optical transport system

Apparatus and method for fibre channel distance extension embedded within an optical transport system

Apparatus for multiplexing Gigabit Ethernet frame and apparatus for demultiplexing 10-Gigabit Ethernet frame

Display device using demultiplexer

Method and apparatus for multiplexing Ethernet channels

Method and apparatus for continuous synchronization of a plurality of asynchronous data sources

Method and apparatus for scanning a data signal based on a direction of phase difference

Methods and apparatus for the hardware implementation of virtual concatenation and link capacity adjustment over SONET/SDH frames

Efficient engine and algorithm for control and data multiplexing/demultiplexing in 5G NR devices