ClassID:

224376

H04J3/0629 - CPC Classification

Classification description:

Time-division multiplex systems; Details; Synchronising arrangements; Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers

Recent Application in this class:
#1
20250233680
2025-07-17

TECHNIQUES FOR ENABLING AND DISABLING OF A SERIALIZER/DESERIALIZER

#2
20250048452
2025-02-06

C-TDMA Protocols, TXOP Sharing Modes For Time Allocation, And Exchange Of Parameters In Multi-AP Systems

#3
20230239062
2023-07-27

Techniques for enabling and disabling of a serializer/deserializer

#4
20230198647
2023-06-22

Active-active TDM PW with asymmetry control

#5
20220209882
2022-06-30

Method and apparatus for switching clock sources

#6
20210119719
2021-04-22

Radio communications

#7
20190280794
2019-09-12

Radio communication repeater, a radio communication system and method

#8
20150140540
2015-05-21

Supporting popularization of information and communications technology in the field of education

#9
20130268814
2013-10-10

Deskew apparatus and method for peripheral component interconnect express

#10
20120287950
2012-11-15

Symmetrical clock distribution in multi-stage high speed data conversion circuits

#11
20100306568
2010-12-02

Symmetrical clock distribution in multi-stage high speed data conversion circuits

#12
20100054384
2010-03-04

Signal delay structure in high speed bit stream demultiplexer

#13
20090324220
2009-12-31

Communication network with node bypassed co-routed multi-channel traffic

#14
20090285239
2009-11-19

Method and apparatus for transmitting and receiving data by using time slicing

#15
20090180580
2009-07-16

Signal transmission system

#16
20090080881
2009-03-26

Optical communication method, optical communication device, and optical communication system

#17
20080175277
2008-07-24

Symmetrical clock distribution in multi-stage high speed data conversion circuits

#18
20080056259
2008-03-06

SWITCH APPARATUS AND SWITCHING METHOD FOR USE IN SAME

#19
20070192651
2007-08-16

Low-speed DLL employing a digital phase interpolator based upon a high-speed clock

#20
20070183462
2007-08-09

Method and apparatus for aligning source data streams in a communications network

#21
20060288250
2006-12-21

Low-speed DLL employing a digital phase interpolator based upon a high-speed clock

#22
20060268941
2006-11-30

Adaptive method for training a source synchronous parallel receiver

#23
20060222005
2006-10-05

Virtual concatenation of PDH signals

#24
20060104223
2006-05-18

System and method to create synchronized environment for audio streams

#25
20060050827
2006-03-09

Synchronization device and semiconductor device

#26
20060002399
2006-01-05

Apparatus for receiving parallel data and method thereof

#27
20050190004
2005-09-01

System and method for tuning output drivers using voltage controlled oscillator capacitor settings

#28
20050015522
2005-01-20

Removing lane-to-lane skew