ClassID:

224875

H04L1/241 - CPC Classification

Classification description:

Arrangements for detecting or preventing errors in the information received; Testing correct operation using pseudo-errors

Recent Application in this class:
#1
20260135646
2026-05-14

METHOD, COMPUTER PROGRAM PRODUCT, AND TEST DEVICE FOR GENERATING A TEST DATA SET FOR TESTING A RECEIVER, AND TEST DATA SET

#2
20250112667
2025-04-03

Receiver Performance Measurement System and Method Thereof

#3
20240322953
2024-09-26

ERROR RATE MEASUREMENT APPARATUS AND ERROR RATE MEASUREMENT METHOD

#4
20220416960
2022-12-29

Testing networked system using abnormal node failure

#5
20220182158
2022-06-09

Margin Test Methods and Circuits

#6
20210126722
2021-04-29

Margin test methods and circuits

#7
20210072287
2021-03-11

Methods for triggering oscilloscopes and oscilloscopes employing the same

#8
20210006341
2021-01-07

Margin test methods and circuits

#9
20190190627
2019-06-20

Margin test methods and circuits

#10
20180279141
2018-09-27

Vehicle communication module and diagnostic device and method for testing thereof

#11
20180248661
2018-08-30

Receiver clock test circuitry and related methods and apparatuses

#12
20170149513
2017-05-25

Margin test methods and circuits

#13
20170093534
2017-03-30

Circuit for introducing signal jitter

#14
20170083422
2017-03-23

Self-error injection technique for point-to-point interconnect to increase test coverage

#15
20170019247
2017-01-19

Redriver link testing

#16
20160344577
2016-11-24

DFE margin test methods and circuits that decouple sample feedback timing

#17
20160233991
2016-08-11

Receiver clock test circuitry and related methods and apparatuses

#18
20150341128
2015-11-26

Margin test methods and circuits

#19
20150124580
2015-05-07

Parameter adjustment method and apparatus

#20
20140331112
2014-11-06

Margin test methods and circuits

#21
20140258795
2014-09-11

Bit error pattern analyzer and method

#22
20130294490
2013-11-07

Receiver clock test circuitry and related methods and apparatuses

#23
20130162279
2013-06-27

Universal test system for testing electrical and optical hosts

#24
20130142226
2013-06-06

SIGNAL TRANSMISSION SYSTEM, SIGNAL TRANSMISSION METHOD AND COMMUNICATION DEVICE

#25
20120140812
2012-06-07

Receiver circuit architectures

#26
20110161747
2011-06-30

Error controlling system, processor and error injection method

#27
20100074314
2010-03-25

Margin test methods and circuits

#28
20100020861
2010-01-28

DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing

#29
20090177457
2009-07-09

Duty cycle distortion (DCD) jitter modeling, calibration and generation methods

#30
20080240219
2008-10-02

Methods and circuits for performing margining tests in the presence of a decision feedback equalizer

#31
20080192640
2008-08-14

Loopback Circuit

#32
20070168770
2007-07-19

System and method for determining on-chip bit error rate (BER) in a communication system

#33
20070033448
2007-02-08

Method and apparatus for using dual bit decisions to measure bit errors and event occurrences

#34
20060227912
2006-10-12

DFE margin test methods and circuits that decouple sample and feedback timing

#35
20060184707
2006-08-17

Error injection

#36
20060143549
2006-06-29

Method and Apparatus for Measuring Bit Error Rate (BER) of Tuner

#37
20060109794
2006-05-25

Communication system

#38
20060107109
2006-05-18

Communication processing apparatus and method and program for diagnosing the same

#39
20060072496
2006-04-06

Memory management in mobile network

#40
20050262402
2005-11-24

Noisy channel emulator for high speed data