224979 ⎘
Arrangements for synchronising receiver with transmitter correction of synchronization errors Correction by a latch cascade
CLOCK DATA RECOVERY CIRCUIT
#2Clock data recovery circuit
#3On-chip synchronous self-repairing system based on low-frequency reference signal
#4Signal receiver and method of measuring offset of signal receiver
#5Clock data recovery circuit
#6SIGNAL RECEIVING CIRCUIT, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SIGNAL RECEIVING CIRCUIT AND SEMICONDUCTOR APPARATUS
#7Real-time eye diagram optimization in a high speed IO receiver
#8Electronic device and method of receiving data
#9Sampler with low input kickback
#10Clock and data recovery for pulse based multi-wire link
#11Read-write data translation technique of asynchronous clock domains
#12Sampler with low input kickback
#13Phase detector in a delay locked loop
#14Semiconductor device
#15Phase difference estimation device and communication device having the phase difference estimation device
#16Apparatus and method for un-delayed decision feedback with sample and hold at selected timing
#17Sampler with low input kickback
#18Clock and data recovery for pulse based multi-wire link
#19Partial response equalizer and related method
#20Interface circuit for high speed communication and system including the same
#21Clock generation circuit and method and semiconductor apparatus and electronic system using the same
#22Electronic circuit and method for transferring data between clock domains
#23Apparatus for processing a serial data stream
#24Integrated circuit incorporating a low power data retiming circuit
#25Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis
#26Clock and data recovery for pulse based multi-wire link
#27Predictive time-to-digital converter and method for providing a digital representation of a time interval
#28Partial response equalizer and related method
#29Synchronization method, and corresponding device and integrated circuit
#30Tracing data from an asynchronous interface
#31Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis
#32High speed current mode latch
#33Bus communication transceiver
#34Differential bang-bang phase detector using standard digital cells
#35Partial response equalizer and related method
#36Receivers and semiconductor systems including the same
#37Data synchronization apparatus
#38High frequency synchronizer
#39Circuits and methods for eliminating reference spurs in fractional-N frequency synthesis
#40Method and apparatus for deskewing data transmissions
#41Signal synchronizing systems and methods
#42SYNCHRONISER CIRCUIT AND METHOD
#43Self-gating synchronizer
#44Partial response equalizer and related method
#45System for synchronizing operation of a circuit with a control signal, and corresponding integrated circuit
#46Circuit devices and methods for re-clocking an input signal
#47Method and apparatus for deskewing data transmissions
#48Command control circuit for semiconductor integrated device
#49SYSTEM AND METHOD FOR SYNCHRONIZING MULTI-CLOCK DOMAINS
#50SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD THEREOF
#51SYSTEMS AND METHODS FOR MULTI-LANE COMMUNICATION BUSSES
#52Domain crossing circuit of a semiconductor memory apparatus
#53Programmable delay circuit providing for a wide span of delays
#54Apparatus and method for transferring a signal from a fast clock domain to a slow clock domain
#55Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bank
#56Method and apparatus for signal synchronizing
#57Network on chip device and on-chip data transmission device
#58System for transmitting data between transmitter and receiver modules on a channel provided with a flow control link
#59Synchronizing modules in an integrated circuit
#60Data transfer system and data processing apparatus
#61Method and circuit for transferring data stream across multiple clock domains
#62Method and apparatus for parsing data streams
#63Self-aligning data path converter for multiple clock systems
#64Clock synchronization circuit
#65Interface for compressed data transfer between host system and parallel data processing system
#66Method and apparatus for fail-safe resynchronization with minimum latency
#67Synchronization between low frequency and high frequency digital signals
#68Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits
#69Synchronizing circuit for stably generating an output signal
#70Synchronizer apparatus for synchronizing data from one clock domain to another clock domain
#71System and method for data phase realignment
#72Picosecond clock synchronization technique for communication and navigation platform equipment
#73Clock data recovery circuitry with programmable clock phase selection