224988 ⎘
Arrangements for synchronising receiver with transmitter; Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT
#2APPARATUS AND MECHANISM TO SUPPORT MULTIPLE TIME DOMAINS IN A SINGLE SOC FOR TIME SENSITIVE NETWORK
#3Trigger signaling through a clock signal in cascading radar systems
#4RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT
#5Reliable link management for a high-speed signaling interconnect
#6Widespread equispatiated phase generation of a clock divided by a non-integer factor
#7Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network
#8Fault-tolerant distribution unit and method for providing fault-tolerant global time
#9Clock phase detection using interior spectral components
#10Apparatus and mechanism to support multiple time domains in a single SoC for time sensitive network
#11Mulit-lane synchronous reset for coherent receivers
#12Transceiver device with real-time clock
#13BASE STATION APPARATUS AND METHOD FOR CONTROLLING BASE STATION APPARATUS
#14Method to improve availability of real-time computer networks
#15Loss of signal detection on CDR
#16Receiver clock test circuitry and related methods and apparatuses
#17Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network
#18Communication device, communication method, and communication system with desynchronization detection
#19Method and system for clock and data recovery (CDR)
#20Fast clock and data recovery for free-space optical communications
#21Base station apparatus and method for controlling base station apparatus
#22Optoelectronic transceiver with power management
#23Clock sustain in the absence of a reference clock in a communication system
#24Receiver clock test circuitry and related methods and apparatuses
#25Receiving device
#26Loss of signal detection on CDR
#27Reception apparatus
#28Internal clock signal control for display device, display driver and display device system
#29Receiver clock test circuitry and related methods and apparatuses
#30Aircraft avionics management and control system
#31Digital to analog converter cell for signed operation
#32Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period
#33Clock and data recovery circuit and method
#34Synchronization system and method for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system which receives periodic transmissions
#35Clock generation apparatus, server system and clock control method
#36Multi-lane re-timer circuit and multi-lane reception system
#37Position-measuring device and method for testing a clock signal
#38Clock recovery circuit, optical receiver, and passive optical network device
#39Resynchronization method of a received stream of groups of bits
#40System and method to detect and communicate loss and retention of synchronization in a real-time data transfer scheme
#41Aircraft avionics management and control system
#42Self-testing integrated circuits
#43Technique for optimizing the phase of a data signal transmitted across a communication link
#44Programmable optical subassemblies and modules
#45Method and algorithm for stabilizing the output state of an optical transceiver
#46Method and apparatus for receiving burst data without using external detection signal
#47Synchronization system and method for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system which receives periodic transmissions
#48Communication system using low bandwidth wires
#49CDR circuit and terminal
#50Low power communication device for scheduling data segments using hold time or lock time of phase locked loop
#51Wireless communication apparatus, mobile wireless communications control method, and wireless station
#52Circuit and methods to use an audio interface to program a device within an audio stream
#53Signal multiplexing device
#54Device and method for preventing lost synchronization
#55Method and apparatus for switching clock frequency in a system-in-package device
#56Method and apparatus for LTE radio link failure determination in DRX mode
#57CDR circuit
#58Clock phase recovery apparatus
#59Synchronization of a receiver to a desired signal
#60Data transmission involving multiplexing and demultiplexing of embedded clock signals
#61Receiver training with cycle slip detection and correction
#62Method, system and device for uplink synchronization
#63Decoupling bang-bang CDR and DFE
#64Signal extender system and signal extender thereof
#65Real time distributed embedded oscillator operating frequency monitoring
#66Data receiver circuit
#67Clock data restoration device
#68Method and apparatus for resilient clock transfer over multiple DSL lines
#69Device for reconstructing the clock of an NRZ signal, and associated transmission system
#70METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS
#71Optical burst mode clock and data recovery
#72Optical network interface, module and engine
#73Transfer apparatus, and jitter control method of transmission signal
#74Synchronization system and method for achieving low power battery operation of a vehicle locating unit in a stolen vehicle recovery system which receives periodic transmissions
#75Method and device for clock data recovery
#76Controlling activation of electronic circuitry of data ports of a communication system
#77Clock data recovery circuit and display device
#78Detecting collisions on multipoint shared optical media
#79Method and apparatus for receiving burst data without using external detection signal
#80Communication system using low bandwidth wires
#81Pulse-Coupled Discrete-Time Phase Locked Loops For Wireless Networks
#82Clock extraction circuit
#83System and method for clock jitter compensation in direct RF receiver architectures
#84Burst mode receiver
#85Method, CAN bus driver and CAN bus system for the recovery of a clock frequency of a CAN bus
#86Frequency synchronization with compensation of phase error accumulation responsive to a detected discontinuity
#87Method and device for clock-data recovery
#88SHARING APPARATUS OF REFERENCE SYNCHRONIZATION SIGNAL AND METHOD THEREOF
#89Method and apparatus for multi-mode clock data recovery
#90Method and apparatus for LTE radio link failure determination in DRX mode
#91System and method for synchronization signal detection and recovery from false triggers
#92Controlling activation of electronic circuitry of data ports of a communication system
#93Clock/data recovery circuit
#94Method and apparatus for handling of clock information in serial link ports
#95Method and apparatus for late timing transition detection
#96Phase lock loop control for digital communication systems
#97Method and system for compensating asymmetrical delays
#98Active/standby switchover method and device of asynchronous backplane in transport network
#99Adaptive synchronization circuit
#100Wireless communication apparatus, mobile wireless communications control method, and wireless station
#101Optical transmission apparatus, optical interface device, and optical transmission method
#102Communication systems and clock generation circuits thereof with reference source switching
#103Cycle slip detection for timing recovery
#104Receiving circuit with adaptive synchronization and method thereof
#105Apparatus and method for transmitting and receiving data bits
#106Clock data restoring device
#107Unidirectional sweep training for an interconnect
#108Short pulse rejection circuit and method thereof
#109High-speed receiver architecture
#110Methods and apparatus for detecting a loss of lock condition in a clock and data recovery system
#111Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern
#112Methods and apparatus for detecting and decoding adaptive equalization training frames
#113Systems and methods for seismic data acquisition employing clock source selection in seismic nodes
#114False frequency lock detector
#115Methods for multi-channel data detection phase locked loop frequency error combination
#116Systems and methods for improved timing recovery
#117TRANSMITTER AND TRANSMITTER/RECEIVER
#118Device and method for preventing lost synchronization
#119Synchronized receiver
#120High-speed receiver architecture
#121Multi-channel timing recovery system
#122Method and apparatus for detecting and compensating for jitter in a communications network
#123Device and Method For Preventing Lost Synchronization
#124Transmission system and transmission apparatus
#125Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity
#126Virtual reference timing for multi-time based systems
#127Selectable loss of signal (LOS) criteria
#128Signal noise filtering in a serial interface
#129Clock recovery circuit and receiver using the circuit
#130Glitch-free clock signal multiplexer circuit and method of operation
#131Detector and method for detecting abnormality in time synchronization
#132Clock regeneration circuit technical field
#133Electronic device for generating secure synchronization signals
#134Sync signal insertion that breaks a maximum bit-run and has a particular detection distance between two or more sync patterns
#135Method and apparatus for controlling transmission frequency in serial advanced technology attachment
#136Clock error detection apparatus and method
#137Sampling clock generator circuit and data receiver using the same
#138Method and apparatus for late timing transition detection
#139Methods and devices for signal synchronization
#140Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM
#141Method and apparatus for handling of clock information in serial link ports
#142Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method
#143Sub-frame synchronized signaling
#144Timing recovery apparatus and method with frequency protection
#145Adaptive equalizer
#146Clock recovery from an optical signal with polarization impairments
#147Clock recovery from an optical signal with dispersion impairments
#148Synchronizing signal generating device and method for serial communication
#149Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
#150Methods of controlling tracker bandwidth in wireless communication systems
#151Configuration of failure and acquire timeouts to facilitate recovery from failures in hierarchical mesh networks
#152Method and apparatus for maintaining a clock/data recovery circuit frequency during transmitter low power mode
#153Clock loss detection and switchover circuit
#154Method and apparatus for multi-mode clock data recovery
#155Clock generation device and clock generation method
#156Controlling a voltage controlled oscillator in a bang-bang phase locked loop
#157Redundant synchronous clock distribution system
#158System and method for synchronization signal detection and recovery from false triggers
#159Data-modulating apparatus, data-modulating method, data-demodulating apparatus, data-demodulating method, and data-providing medium
#160Method and apparatus for a digital-to-phase converter
#161Data processing device including clock recovery from various sources
#162Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method
#163Clock switching circuit
#164Circuit arrangement and method to provide error detection for multi-level analog signals, including 3-level pulse amplitude modulation (PAM-3) signals
#165Symbol timing search algorithm
#166False lock detection circuit and false lock detection method, PLL circuit and clock data recovery method, communication device and communication method, and optical disk reproducing device and optical disk reproducing method
#167Burst mode clock and data recovery frequency calibration
#168Signal detector
#169Controlling a voltage controlled oscillator in a bang-bang phase locked loop
#170Method and device for the sampling of digital data in synchronous transmission, with maintenance of binary integrity
#171Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
#172Methods and apparatus for monitoring frequency corrections in a clock and data recovery phase-lock loop, and for deriving operating indications therefrom
#173Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
#174Method to synchronize data and a transmitter and a receiver realizing said method
#175Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
#176Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
#177Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
#178Method and apparatus for modulating and demodulating data into a variable-length code and providing a sync signal to the train of codes
#179Highly scalable methods and apparatus for multiplexing signals
#180Method for resynchronization of a mobile radio receiver in the event of a changeover between two different modulation methods
#181Clock recovery system for encoded serial data with simplified logic and jitter tolerance
#182Device for reconstructing data from a received data signal and corresponding transceiver
#183Synchronizing RF system
#184Method for correcting the scanning start of a serial bit sequence of an output signal of a filter
#185Synchronizing unit for redundant system clocks
#186Semiconductor integrated circuit device and method of testing the same
#187Adaptive lock position circuit
#188Clock loss detection and switchover circuit
#189Semiconductor integrated circuit and receiver device
#190Clock-data recovery circuit with metastability detection and resolution
#191Mitigating interaction between adaptive equalization and timing recovery in multi-rate receiver
#192Sampling phase adjustment device and adjusting method thereof
#193Reliable precision time architecture
#194Synchronization of multiple encoders for streaming content
#195Extender and method of recovering differential signal
#196Serial link training method and apparatus with deterministic latency