225000 ⎘
Arrangements for synchronising receiver with transmitter; Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector
Low power edge and data sampling
#2Low power edge and data sampling
#3Methods and devices for asymmetric frequency spreading
#4Clock data recovery
#5Clock data recovery unit
#6Radio frequency clocked device
#7Clock data recovery
#8Low power edge and data sampling
#9Phase difference detectors and devices for detecting phase difference between oscillation signals
#10Duty cycle estimation
#11Jitter sensing and adaptive control of parameters of clock and data recovery circuits
#12Clock data recovery device
#13Jitter sensing and adaptive control of parameters of clock and data recovery circuits
#14Low power edge and data sampling
#15Data-driven phase detector element for phase locked loops
#16Multi-rate transceiver circuitry
#17Skew management for PAM communication systems
#18Digital duty cycle correction for frequency multiplier
#19Clock and data recovery circuit and phase interpolator therefor
#20SELF-TEST FOR SOURCE-SYNCHRONOUS INTERFACE
#21Digital system for estimating signal non-energy parameters using a digital phase locked loop
#22Self-adapting phase-locked loop filter for use in a read channel of a heat assisted magnetic recording drive
#23Unequalized clock data recovery for serial I/O receiver
#24Data alignment implemented in a field programmable gate array (FPGA) device
#25Clock data recovery apparatus and method and phase detector
#26Phase locked loop, wireless communication apparatus and wireless communication method
#27Wireless communication apparatus, integrated circuit and wireless communication method
#28Integrated circuit incorporating a low power data retiming circuit
#29Dual path timing wander removal
#30Dual path timing jitter removal
#31Digital system for estimating signal non-energy parameters using a digital phase locked loop
#32Phase locked loop (PLL) architecture
#33Four-phase clock generator with timing sequence self-detection
#34Influence clock data recovery settling point by applying decision feedback equalization to a crossing sample
#35Adaptive analog-to-digital conversion based on signal prediction
#36Phase interpolator calibration
#37Phase adjustment circuit for clock and data recovery circuit
#38Multi-rate transceiver circuitry
#39QUADRICORRELATOR CARRIER FREQUENCY TRACKING
#40Multi-channel timing recovery device
#41CDR circuit and semiconductor device
#42SEMICONDUCTOR DEVICE
#43Wireless device and method for controlling wireless device
#44Systems and methods for measuring power and impedance in wireless power charging systems
#45Symbol clock recovery circuit
#46Multi-rate transceiver circuitry
#47Referenceless clock and data recovery circuit
#48Unequalized clock data recovery for serial I/O receiver
#49Fast settling mixed signal phase interpolator with integrated duty cycle correction
#50Sensor subassembly and method for sending a data signal
#51Differential bang-bang phase detector using standard digital cells
#52Phase interpolator calibration
#53Lock detector for phase-locked loop
#54Data reception apparatus and method of determining identical-value bit length in received bit string
#55Unequalized clock data recovery for serial I/O receiver
#56Multiphase receiver with equalization circuitry
#57Apparatus, system, and method for timing recovery
#58Low power edge and data sampling
#59Multiphase receiver with equalization circuitry
#60Receiver and method of receiving signal for reducing intersymbol interference
#61CDR CIRCUIT, RECEIVER, AND TRANSMITTING-RECEIVING SYSTEM
#62Apparatus, system, and method for timing recovery
#63Integrating receiver with precharge circuitry
#64Multiphase receiver with equalization
#65Memory device receiver
#66Receiving a Signal in a Communication System
#67Method and apparatus for adaptively establishing a sampling phase for decision-feedback equalization
#68Clock and data recovery with extended integration cycles
#69Clock-free activation circuit
#70Method and apparatus for generating reference voltage to adjust for attenuation
#71Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
#72Low latency multi-level communication interface
#73Method and apparatus for receiving high-speed signals with low latency
#74Parallel DSP demodulation for wideband software-defined radios
#75Maximum likelihood bit synchronizer and data detector
#76Method and apparatus for calibrating a multi-level current mode driver having a plurality of source calibration signals
#77Clock data recovery
#78Iterative recovery from baseline or timing disturbances
#79Iterative recovery from baseline or timing disturbances
#80Analog-to-digital conversion based on signal prediction
#81Clock data recovery circuit
#82Dual-mode non-return-to-zero (NRZ)/ four-level pulse amplitude modulation (PAM4) receiver with digitally enhanced NRZ sensitivity
#83Methods and systems for estimating skew
#84Self-adapting phase-locked loop filter for use in a read channel
#85Low-noise flexible frequency clock generation from two fixed-frequency references
#86Fractional-N PLL-based CDR with a low-frequency reference