KALMAN FILTER BASED PHASE-LOCKED LOOP WITH RE-ENCODING BASED PHASE DETECTOR

System and method for demodulation and decoding a data body of a power line communication

RECEIVER, OPERATION METHOD THEREOF, AND MEMORY DEVICE

TWO-POINT SAMPLING OPTIMIZATION METHOD AND SYSTEM FOR SINUSOIDAL EXCITATION-BASED FREQUENCY RESPONSE MEASUREMENT

Method for monitoring a radio frequency receiver and semiconductor device

State estimation for time synchronization

Receiver with enhanced clock and data recovery

Synchronization mechanism for high speed sensor interface

Phase detection method, phase detection circuit, and clock recovery apparatus

Clock data recovery mechanism

Receiver with enhanced clock and data recovery

Multi-level signal clock and data recovery

Low power high speed receiver with reduced decision feedback equalizer samplers

Synchronization mechanism for high speed sensor interface

USER TERMINAL AND RADIO COMMUNICATION METHOD

Electronic circuit configured to adjust skew between clock signals

TIMING RECOVERY FOR NYQUIST SHAPED PULSES

Receiver with enhanced clock and data recovery

Phase detectors for clock and data recovery

SIGNAL RECEIVER WITH MULTI-LEVEL SAMPLING

Synchronization mechanism for high speed sensor interface

METHOD AND DRIVER CIRCUIT FOR RESONANT ANTENNA CIRCUIT

Multi-level clock and data recovery circuit

Circuit and method for processing data

Multi-layer time-interleaved analog-to-digital convertor (ADC)

Parallel-serial conversion circuit, information processing apparatus and timing adjustment method

Serial data multiplexing

SELF-TEST FOR SOURCE-SYNCHRONOUS INTERFACE

Receiver with enhanced clock and data recovery

Transmitting device for high speed communication, interface circuit and system including the same

Superposed signal sampling apparatus and sampling method

Phase locked loop, wireless communication apparatus and wireless communication method

Sampling circuit, sampling method, sampling oscilloscope, and waveform display method

TRANSMITTING DEVICE FOR HIGH SPEED COMMUNICATION, INTERFACE CIRCUIT AND SYSTEM INCLUDING THE SAME

Multi-input wireless receiver based on RF sampling techniques

Low power high speed receiver with reduced decision feedback equalizer samplers

At-rate SERDES clock data recovery with controllable offset

Optical transceiver of flexible modulation format

Phase adjustment circuit for clock and data recovery circuit

Phase detector and retimer for clock and data recovery circuits

Symbol clock recovery circuit

Method of generating clock and semiconductor device

Apparatus for generating quadrature clock phases from a single-ended odd-stage ring oscillator

At-rate SERDES clock data recovery with controllable offset

Synchronisation method and device for transmit and receive symbols of all-digital receiver

Data receivers and methods of implementing data receivers in an integrated circuit

Signal processing device and signal processing method

Signal receiver with multi-level sampling

Digital signal sampling method

Systems and methods for filtering a received signal to remove intersymbol interference

Receiver circuit and semiconductor integrated circuit

Signal receiver with multi-level sampling

Method and circuit for clock recovery of a data stream description

Multi-layer time-interleaved analog-to-digital convertor (ADC)

Systems and methods for pattern detection

Clock recovery apparatus and method thereof

Symbol clock recovery circuit

Communication receiver and a receiving method

Clock data recovery circuit and clock data recovery method

Systems and Methods for ADC Sample Based Timing Recovery

System and method for packet communication

Phase detection method and circuit

Digital receivers

Clock-data-recovery technique for high-speed links

Method and device for multi-dimensional processing using a single-state decision feedback equalizer

PHASE COMPARATOR, PLL CIRCUIT, INFORMATION REPRODUCTION PROCESSING DEVICE, OPTICAL DISK PLAYBACK DEVICE AND MAGNETIC DISK PLAYBACK DEVICE

Multi-pair gigabit ethernet transceiver

SYNCHRONOUS CONTROL CIRCUIT AND VIDEO DISPLAY DEVICE

Clock regeneration circuit and receiver using the same

PHY control module for a multi-pair gigabit transceiver

Multi-pair gigabit ethernet transceiver having adaptive disabling of circuit elements

Receiver with enhanced clock and data recovery

System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system

Low jitter and high bandwidth clock data recovery

ETHERNET SYSTEM

Demodulator for a multi-pair gigabit transceiver

DYNAMIC REGULATION OF POWER CONSUMPTION OF A HIGH-SPEED COMMUNICATION SYSTEM

Data recovery circuit, data recovery method and data receiving apparatus

High-speed decoder for a multi-pair gigabit transceiver

Physical coding sublayer for a multi-pair gigabit transceiver

Method and apparatus for low power simultaneous frequency, automatic gain control and timing acquisition in radio receivers

Frequency detector and phase locked loop having the same

Multi-pair gigabit Ethernet transceiver

Multi-pair gigabit ethernet transceiver

Apparatus and method for recovering data

Apparatus for, and method of, processing signals transmitted over a local area network

System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system

PHY control module for a multi-pair gigabit transceiver

System and method for trellis decoding in a multi-pair transceiver system

Symbol timing recovery circuit

Signal processing circuit

Dynamic regulation of power consumption of a high-speed communication system

Multi-pair gigabit ethernet transceiver

Systems and arrangements for clock and data recovery in communications

Systems and arrangements for clock and data recovery in communications

Phase error correction circuit and receiver incorporating the same

Device And Method For Detecting Symbol Timing For Highly Bandwidth Efficient High Order Modulation System

SEQUENCE DECISION FEEDBACK EQUALIZER

Multi-pair gigabit ethernet transceiver

Clock regeneration circuit technical field

Data recovery apparatus and method for reproducing recovery data

SYMBOL TIMING DETECTOR AND WIRELESS TERMINAL

Multi-pair gigabit ethernet transceiver having a single-state decision feedback equalizer

Methods for adjusting sampling clock of sampling circuit and related apparatuses

High definition multi-media interface

Multi-pair gigabit ethernet transceiver having decision feedback equalizer

Multi-pair gigabit Ethernet transceiver having adaptive disabling of circuit elements

Timing recovery system for a multi-pair gigabit transceiver

Method and system for providing timing recovery in an optical system

Method of symbol timing synchronization in communication systems

System and method for executing preamble detection, symbol timing recovery, and frequency offset estimation

Phase detection device and method thereof

Bit-detection arrangement and apparatus for reproducing information

Data-level clock recovery

Interface circuit for a media access controller and an optical line termination transceiver module

Clock and data timing compensation for receiver

High-speed decoder for a multi-pair gigabit transceiver

Clock reproduction circuit

Eye center determination system and method

Receiver having digital timing recovery function

Data sampler for digital frequency/phase determination

Symbol position detection device and symbol position detection method

Image data decoding method of image vertical blanking interval and a device thereof

Timing bias compensation for a data receiver with decision-feedback equalizer

Method and device for digitally measuring the phase of a signal

Method and apparatus for adjusting phase of sampling frequency of ADC

Data transmission device and data transmission method

Phase error detecting circuit and synchronization clock extraction circuit

Apparatus for timing recovery and method thereof

System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system

Dynamic register with IDDQ testing capability

Methods and devices for obtaining sampling clocks

Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods

Symbol timing search algorithm

PHY control module for a multi-pair gigabit transceiver

Programmable phase interpolator adjustment for ideal data eye sampling

Physical coding sublayer for a multi-pair gigabit transceiver

Pair-swap independent trellis decoder for a multi-pair gigabit transceiver

Data-level clock recovery

PHY control module for a multi-pair gigabit transceiver

Ethernet transceiver with single-state decision feedback equalizer

Transition tracking

Bit-detection arrangement and apparatus for reproducing information

Dynamic regulation of power consumption of a high-speed communication system

Dynamic register with IDDQ testing capability

Apparatus for transmitting and receiving data

Clock recovery for PAM4 signaling using bin-map

Synchronization between data and clock signals in high-speed interfaces

Method and apparatus for multi-level signaling adaptation with fixed reference levels

Clock data recovery apparatus and operation method thereof

System and method for multi-level amplitude modulation and demodulation

Semiconductor integrated circuit and receiver

Systems and methods for clock and data recovery

Systems and methods for clock and data recovery

Method for symbol clock recovery in pulse position modulation (PPM) systems

Method and system for synthetically sampling input signal