225004 ⎘
Arrangements for synchronising receiver with transmitter; Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop; Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
Wideband phase-locked loop for delay and jitter tracking
#2Phase detection method, phase detection circuit, and clock recovery apparatus
#3Phase control block for managing multiple clock domains in systems with frequency offsets
#4Trigger circuitry for fast, low-power state transitions
#5Phase rotator
#6Phase control block for managing multiple clock domains in systems with frequency offsets
#7Serial transmitter with feed forward equalizer
#8Circuits for amplitude demodulation and related methods
#9Clock recovery circuit, semiconductor integrated circuit device, and radio frequency tag
#10Method and system for synchronizing and interleaving separate sampler groups
#11Device and method for skew compensation between data signal and clock signal
#12Data recovery using edge detection
#13Phase control block for managing multiple clock domains in systems with frequency offsets
#14Transmission apparatus and clock regeneration method
#15Apparatus and methods for burst mode clock and data recovery for high speed serial communication links
#16Oversampling CDR which compensates frequency difference without elasticity buffer
#17Data storage element and signal processing method
#18Oversampling CDR which compensates frequency difference without elasticity buffer
#19System and apparatus for clock retiming with catch-up mode and associated methods
#20Clock and data recovery with high jitter tolerance and fast phase locking
#21Oversampling CDR which compensates frequency difference without elasticity buffer
#22Baud rate phase detector with no error latches
#23Point to multi-point clock-forwarded signaling for large displays
#24Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data
#25Synchronous data system and method for providing phase-aligned output data
#26Receiver and transmission and reception system
#27Delay-locked loop with independent phase adjustment of delayed clock output pairs
#28Receiving apparatus, transmission and reception system, and restoration method
#29Clock and data recovery circuit and parallel output circuit
#30Apparatus and method for recovering burst-mode pulse width modulation (PWM) and non-return-to-zero (NRZ) data
#31Method, system and device for removing media access control addresses
#32Massively parallel supercomputer
#33Synchronization circuit and synchronization method
#34Data recovery apparatus and method by using over-sampling
#35Level transition determination circuit and method for using the same
#36Frequency detector and method for detecting frequencies
#37Receive timing manager
#38Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications
#39Oversampling circuit, serial communication apparatus and oversampling method
#40Glitch free oversampling clock and data recovery
#41RECEPTION APPARATUS
#42Waveform generator in a multi-chip system
#43Global Navigation Satellite System (GLONASS) data bit edge detection
#44Parallel synchronizing cell with improved mean time between failures
#45Synchronous sequential processing of multi-sampled phase
#46Clock and data recovery for burst-mode serial signals
#47Clock hand-off circuit
#48Simplifying and speeding the management of intra-node cache coherence
#49Delay control circuit and method
#50SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD THEREOF
#51Apparatus and methods for differential signal receiving
#52Method and system for bit detection and synchronization
#53Asynchronous data recovery methods and apparatus
#54BIT IDENTIFICATION CIRCUIT
#55Data recovery circuit
#56Domain crossing circuit of a semiconductor memory apparatus
#57CLOCK PHASE ALIGNING APPARATUS FOR BURST-MODE DATA
#58Electronic device, integrated circuit and method therefor
#59Techniques for asynchronous data recovery
#60Fast powering-up of data communication system
#61Method for Data Synchronization
#62Managing coherence via put/get windows
#63Phase control block for managing multiple clock domains in systems with frequency offsets
#64DATA ALIGNMENT SYSTEM AND METHOD FOR DOUBLE DATA RATE INPUT DATA STREAM
#65Differential transmitter and auto-adjustment method of data strobe thereof
#66Massively parallel supercomputer
#67DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION
#68Pulse signal reception device, pulsed QPSK signal reception device, and pulse signal reception method
#69Instant-acquisition clock and data recovery systems and methods for serial communications links
#70Sampling method and data recovery circuit using the same
#71METHOD, NETWORK, APPARATUS AND COMPUTER PROGRAM FOR USING LEAKY COUNTERS IN CLOCK AND DATA RECOVERY CIRCUITS
#72Method and apparatus for jitter compensation in receiver circuits using nonlinear dynamic phase shifting technique based on bit history pattern
#73Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications
#74Systems and methods for data recovery in an input circuit receiving digital data at a high rate
#75Serial Data Sampling Point Control
#76Data capture technique for high speed signaling
#77Interface circuit as well as method for receiving and/or for decoding data signals
#78Clock data recovery circuit
#79Synchronous digital data transmission interface
#80Electric circuit for and method of generating a clock signal
#81Method and circuit for local clock generation and smartcard including it thereon
#82Single loop frequency and phase detection
#83Method and Apparatus for the Capture of Serial Data Amid Jitter
#84Data recovery circuits using oversampling for best data sample selection
#85Receiver circuit and receiving method
#86Efficient implementation of multidimensional fast fourier transform on a distributed-memory parallel multi-node computer
#87Determining oversampled data to be included in unit intervals
#88Optimized scalable network switch
#89APPARATUS AND RELATED METHOD FOR DETECTING PHASE OF INPUT DATA
#90System and method for utilizing a phase interpolator to support a data transmission procedure
#91Method and apparatus for reception of data over a transmission link
#92Oversampling circuit and oversampling method
#93Receiving a Signal in a Communication System
#94Multi-bit-rate optical communication method, optical network unit, and optical line terminal
#95Phase selector for data transmitting device
#96Data recovery apparatus and method for reproducing recovery data
#97Phase interpolator
#98Apparatus and method for retiming data using phase-interpolated clock signal
#99Time stamping events for fractions of a clock cycle
#100Clock generator and clock recovery circuit utilizing the same
#101Reconfigurable direct RF bandpass sampling receiver and related methods
#102Adaptive reception techniques for over-sampled receivers
#103Managing coherence via put/get windows
#104Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits
#105Multiphase clock recovery
#106Asynchronous data reception without precision timing reference
#107Digital signal processing of multi-sampled phase
#108Methods and apparatus for bit synchronizing data transferred across a multi-pin asynchronous serial interface
#109Receive timing manager
#110Method for sampling reverse data and a reverse data sampling circuit for performing the same
#111High-speed serial transceiver with sub-nominal rate operating mode
#112Methods and apparatus for synchronizing data transferred across a multi-pin asynchronous serial interface
#113Method of capturing data transferred in synchronization with a data strobe signal and data capture circuit performing same
#114Dynamic recalibration mechanism for elastic interface
#115Error correction of balanced codeword sequence
#116Method and apparatus for reception of data over digital transmission link
#117Clock and data recovery apparatus and method thereof
#118Data recovery circuits using oversampling for best data sample selection
#119Clock generator and data recovery circuit using the same
#120Detector for clock phase and carrier phase
#121Clock and data recovery systems and methods
#122Circuits and methods for recovering a clock signal
#123Data recovery circuits using oversampling for maverick edge detection/suppression
#124Clock recovery
#125Slave device
#126Network interface using programmable delay and frequency doubler
#127Data receiver with servo controlled delayed clock
#128Latch and phase synchronization circuit using same
#129High-speed serial link clock and data recovery
#130Data recovery method and data recovery circuit
#131IMPROVEMENTS TO DATA RECOVERY CIRCUITS USING OVERSAMPLING FOR ISI COMPENSATION
#132Multichannel communications link receiver having parallel optical components
#133Clock recovery system for encoded serial data with simplified logic and jitter tolerance
#134Data receiving device
#135Maximum likelihood bit synchronizer and data detector
#136Multiple-phase switching circuit
#137System and method for data phase realignment
#138System for generating multi phase clocks across wide frequency band using tunable passive polyphase filters
#139Clock data recovery apparatus and operation method thereof
#140Systems and methods for clock and data recovery
#141Systems and methods for clock and data recovery
#142Serial transmitter with feed forward equalizer and timing calibration
#143Serial transmitter with feed forward equalizer