225011 ⎘
Arrangements for synchronising receiver with transmitter; Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
Synchronizing a device that has been power cycled to an already operational system
#2Adaptive equalization using correlation of data patterns with errors
#3Synchronizing a device that has been power cycled to an already operational system
#4Adaptive equalization using correlation of data patterns with errors
#5Adaptive equalization correlating data patterns with transition timing
#6Operating state machine controllers after powering, decoupling, monitoring, coupling communications
#7Adaptive equalization using correlation of data patterns with errors
#8Bi-phase communication demodulation techniques
#9Adaptive equalization using correlation of data patterns with errors
#10Clock regeneration circuit, semiconductor integrated circuit device and RF tag
#11Monitoring communication link in powered-up device for synchronization point sequence
#12System and method for reducing false preamble detection in a communication receiver
#13Unidirectional clock signaling in a high-speed serial link
#14System and method for master-slave data transmission based on a flexible serial bus for use in hearing devices
#15Adaptive equalization using correlation of edge samples with data patterns
#16Bi-phase communication demodulation techniques
#17Target system recognizing synchronization point sequence on mode select input
#18Method and apparatus for detecting a set up signal used for data communication over a communication network
#19Operating two tap system after detecting shared bus synchronization sequence
#20Data reception apparatus oversampling received bits and data communication system oversampling received bits
#21Method and device for sending upstream transfer frame in passive optical network
#22Adaptive equalization using correlation of edge samples with data patterns
#23Carrier selection for multiple antennas
#24Method and apparatus for receiving burst data without using external detection signal
#25Adapter power up circuitry forcing tap states and decoupling tap
#26Apparatus for transmitting and receiving signal in communication system
#27Adapter circuitry resetting scan test logic to mandatory feature set
#28BAUD RATE TIMING RECOVERY FOR NYQUIST PATTERNS IN A COMMUNICATION SYSTEM
#29Method for enabling AC coupling of high-speed burst data signals transmitted in optical networks
#30Preamble design for supporting multiple topologies with visible light communication
#31Device for receiving a digital signal
#32Adaptive equalization using correlation of edge samples with data patterns
#33Bi-phase communication demodulation techniques
#34Systems and methods for pattern detection
#35Signal Calibration Method and Client Circuit and Transmission System Using the Same
#36Sampling clock selection module of serial data stream
#37Symbol clock recovery circuit
#38Adapter and scan test logic synchronizing from idle state
#39Partial-rate transfer mode for fixed-clock-rate interface
#40Carrier selection for multiple antennas
#41Transmission apparatus, transmission method, reception apparatus, and reception method
#42Methods and apparatus for trimming of CDR clock buffer using histogram of clock-like data pattern
#43Communication receiver and a receiving method
#44Preamble detection at low signal-to-noise levels
#45Timing Error Correction System and Method
#46Adaptor detecting sequence on TMS and coupling TAP to TCK
#47Method and device for sending upstream transfer frame in passive optical network
#48Synchronizing remote devices with synchronization sequence on JTAG control lead
#49Method and device for sending upstream transfer frame in passive optical network
#50Synchronization signal detection apparatus
#51Low power intermittent messaging for hearing assistance devices
#52Low power intermittent messaging for hearing assistance devices
#53Preamble design for supporting multiple topologies with visible light communication
#54Communication system including a data bus and multiple user nodes connected thereto, and method for operating such a communication system
#55Clock and data recovery circuit of a source driver and a display device
#56Method and apparatus for detecting a set up signal used for data communication over a communication network
#57Clock data recovery circuit and display device
#58Serial bus clock frequency calibration system and method thereof
#59Method and apparatus for receiving burst data without using external detection signal
#60Method and circuit for trimming an internal oscillator of a USB device
#61Transmission device, receiving device and communication system
#62Automatic frequency correction
#63Detection of frame marker quality
#64Edge-based sampler offset correction
#65SYNCHRONOUS PROCESSING APPARATUS, RECEIVING APPARATUS AND SYNCHRONOUS PROCESSING METHOD
#66Adaptive equalization using correlation of edge samples with data patterns
#67Signal processing apparatus and signal processing method
#68Frame synchronisation scheme with interference reduction
#69Method capable of avoiding data error from incorrect sampling points
#70Serial bus clock frequency calibration system and method thereof
#71Low-power clock generation and distribution circuitry
#72High-Speed Low-Power Differential Receiver
#73Apparatus and method for acquiring frame synchronization and frequency synchronization simultaneously in communication system
#74Clockless transmission system and clockless transmission method
#75Clock generating device and method thereof
#76Synchronization determining circuit, receiver including the synchronization determining circuit, and method of the receiver
#77Narrow band receiver
#78Method for Synchronising Components of a Motor Vehicle Brake System and Electronic Brake Control System
#79FREQUENCY-LOCKING DEVICE AND FREQUENCY-LOCKING METHOD THEREOF
#80Code division multiplex communication system
#81Data transfer device and electronic camera
#82Partial-rate transfer mode for fixed-clock-rate interface
#83Bit synchronization circuit with phase tracking function
#84Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal
#85Data sampling circuit and method for clock and data recovery
#86Clock and data recovery circuits
#87Receiving apparatus and method
#88Bit pattern synchronization in acquired waveforms
#89Gain control for reduced interframe spacing (RIFS)
#90Carrier selection for multiple antennas
#91Dynamic receiver filter adjustment across preamble and information payload
#92Powering up adapter and scan test logic TAP controllers
#93Synchronizing TAP controllers with sequence on TMS lead
#94Training pattern for a biased clock recovery tracking loop
#95Bias and random delay cancellation
#96Combined alignment scrambler function for elastic interface
#97Serial digital data communication interface for transmitting data bits each having a width of multiple clock cycles
#98Phase error correction circuit and receiver incorporating the same
#99Method and apparatus for clock skew calibration in a clock and data recovery system using multiphase sampling
#100Data stream processing method and system
#101Reliable packet detection in a wireless receiver when packets contain a known repetitive sequence
#102Serial communication system with baud rate generator
#103Adaptive equalization using correlation of edge samples with data patterns
#104Apparatus for performing alternating quadratures differential binary phase shift keying modulation and demodulation
#105Ring-connected surveillance system with real-time backup monitoring
#106Sub-frame synchronized multiplexing
#107Clock generation circuit
#108Serial transfer interface
#109Clock and data recovery wherein an FB-DIMM is connected to signal path and null and sync frames control the FB-DIMM
#110Method and an apparatus to reduce electromagnetic interference
#111Bit synchronization circuit with phase tracking function
#112Wireless receiving device having low power consumption and excellent reception performance
#113Method and apparatus for synchronization of data in a transformer circuit
#114Synchronous one-bit interface protocol or data structure
#115Receiving apparatus and synchronising method for a digital telecommunication system
#116Single-VCO CDR for TMDS data at gigabit rate
#117Receiver having digital timing recovery function
#118Combined alignment scrambler function for elastic interface
#119Digital video signal processing apparatus and method for extracting data in a vertical blanking interval
#120Data transmission system and data transmission device
#121Data processing apparatus that processes incoming bits
#122Preamble aided synchronization
#123Training pattern for a biased clock recovery tracking loop
#124CMOS burst mode clock data recovery circuit using frequency tracking method
#125Communication controller with automatic time stamping
#126Method and device for extracting a clock frequency underlying a data stream
#127Communication apparatus and communication method
#128Data processing apparatus that identifies a communication clock frequency
#129Frame synchronisation scheme with interference reduction
#130Ultra-wideband communication protocol
#131Carrier detecting method and carrier detecting circuit
#132Rapid discrimination preambles and methods for using the same
#133Apparatus for burst and timing synchronization in high-rate indoor wireless communication
#134Pass through debug port on a high speed asynchronous link
#135Serial data transferring apparatus
#136Ultra-wideband communication protocol
#137Packet-based optical communications networks
#138Data transmission system
#139Device for calibrating a clock signal
#140Preamble detection during acquisition
#141Method for symbol clock recovery in pulse position modulation (PPM) systems