Austin, Texas
United States
50
2025-10-30
The entities that hold a legal rights for patent applications filed by inventor THYAGARAJAN Sriram:
Sriram THYAGARAJAN from Austin, US has applied for patents for these inventions. The list has both pending applications and granted patents:
CELL ARRANGEMENT FOR SEMICONDUCTOR DEVICE LAYOUT
#2 | 2025-05-29Systems, Methods, and Devices for a Wordline or a Bitline Formed and Disposed Within a Backside Metal Layer
#3 | 2025-05-01Dual Wordline Applications in Memory
#4 | 2025-03-27POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE
#5 | 2025-01-09Skew Cell Architecture
#6 | 2024-07-11Multi-Port Bitcell Architecture
#7 | 2024-07-04Multi-port circuit architecture
#8 | 2024-04-25Multi-port bitcell architecture
#9 | 2024-01-11Circuitry for memory address collision prevention
#10 | 2023-12-21Circuits and Methods for I/O Circuitry TSV Coupling
#11 | 2023-12-21Multi-port memory architecture
#12 | 2023-05-04Flexible sizing and routing architecture
#13 | 2022-10-06Wordline modulation techniques
#14 | 2022-09-29Metal routing techniques
#15 | 2022-09-15Buried Power Rail Architecture
#16 | 2022-08-11Memory architecture with DC biasing
#17 | 2022-04-21Backside power supply techniques
#18 | 2022-04-21Power-gating techniques with buried metal
#19 | 2022-03-17Backside power rail architecture
#20 | 2022-03-10Buried metal technique for critical signal nets
#21 | 2022-03-10Cell architecture
#22 | 2022-03-03Frontside-to-backside intermixing architecture for coupling a frontside network to a backside network
#23 | 2022-03-03Buried power rail structure for providing multi-domain power supply for memory device
#24 | 2021-12-16Memory compiler techniques
#25 | 2021-10-28Slew-load characterization
#26 | 2021-09-23Bitcell with multiple read bitlines
#27 | 2021-08-05Configurable control of integrated circuits
#28 | 2021-06-24Memory multiplexing techniques
#29 | 2021-03-04Read and write techniques
#30 | 2021-01-21Computer implemented system and method for generating a layout of a cell defining a circuit component
#31 | 2020-12-10Control architecture for column decoder circuitry
#32 | 2020-09-10Transistor gate arrangement to modify driver signal characteristics
#33 | 2020-07-09Memory structure with multi-cell poly pitch
#34 | 2020-04-30Apparatus and method to access a memory location
#35 | 2020-04-23Metal layout techniques
#36 | 2020-03-05Transistor gate arrangement to modify driver signal characteristics
#37 | 2019-12-31Segmented memory instances
#38 | 2019-10-24Multi-port memory circuitry
#39 | 2019-01-24Computer implemented system and method for generating a layout of a cell defining a circuit component
#40 | 2019-01-03Circuit with impedance elements connected to sources and drains of pMOSFET headers
#41 | 2018-11-08Inverter circuitry
#42 | 2018-08-09Computer implemented system and method for generating a layout of a cell defining a circuit component
#43 | 2018-06-21Corner database generator
#44 | 2017-04-27Location-based optimization for memory systems
#45 | 2016-03-08Test techniques in memory devices
#46 | 2016-02-04Access suppression in a memory device
#47 | 2015-05-21Computer implemented system and method for generating a layout of a cell defining a circuit component
#48 | 2015-02-19Memory access control in a memory device
#49 | 2015-01-08Memory having power saving mode
#50 | 2010-08-05ROM array
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