Inventor profile of:

Roman Pletka

City:

Uster

Country:

Switzerland

Published Applications:

23

Last publication date:

2019-09-12

Top Assignees for applications by Roman Pletka

The entities that hold a legal rights for patent applications filed by inventor Pletka Roman:

Recent patent applications by Pletka Roman

Roman Pletka from Uster, CH has applied for patents for these inventions. The list has both pending applications and granted patents:

#1 | 2019-09-12
US20190278643A1
Physics

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

#2 | 2019-09-05
US20190272232A1
Physics

Non-volatile memory controller cache architecture with support for separation of data streams

#3 | 2019-04-11
US20190107959A1
Physics

Techniques for retention and read-disturb aware health binning

#4 | 2018-10-30
US15667485
Physics

Reducing read disturb effect on partially programmed blocks of non-volatile memory

#5 | 2018-10-16
US15613240
Physics

Mitigating read errors following programming in a multi-level non-volatile memory

#6 | 2017-12-07
US20170351614A1
Physics

Non-volatile memory controller cache architecture with support for separation of data streams

#7 | 2017-07-27
US20170212692A1
Physics

Reducing read access latency by straddling pages across non-volatile memory channels

#8 | 2017-06-29
US20170185298A1
Physics

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

#9 | 2017-05-04
US20170123660A1
Physics

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

#10 | 2017-03-30
US20170091006A1
Physics

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

#11 | 2016-06-30
US20160188478A1
Physics

MANAGING METADATA FOR CACHING DEVICES DURING SHUTDOWN AND RESTART PROCEDURES

#12 | 2016-06-23
US20160179678A1
Physics

Non-volatile memory controller cache architecture with support for separation of data streams

#13 | 2016-06-23
US20160179412A1
Physics

Endurance enhancement scheme using memory re-evaluation

#14 | 2016-06-16
US20160170870A1
Physics

Non-volatile memory system having an increased effective number of supported heat levels

#15 | 2016-05-19
US20160141048A1
Physics

Background threshold voltage shifting using base and delta threshold voltage shift values in non-volatile memory

#16 | 2016-05-12
US20160132392A1
Physics

Non-volatile memory data storage with low read amplification

#17 | 2016-04-21
US20160110124A1
Physics

Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management

#18 | 2016-03-31
US20160092352A1
Physics

Reducing write amplification in solid-state drives by separating allocation of relocate writes from user writes

#19 | 2016-02-02
US14500900
Physics

Background threshold voltage shifting using base and delta threshold voltage shift values in flash memory

#20 | 2015-03-05
US20150067271A1
Physics

Selectively enabling write caching in a storage system based on performance metrics

#21 | 2015-01-08
US20150012706A1
Physics

Managing metadata for caching devices during shutdown and restart procedures

#22 | 2012-11-29
US20120303878A1
Physics

Method and Controller for Identifying a Unit in a Solid State Memory Device for Writing Data to

#23 | 2012-11-29
US20120303860A1
Physics

Method and controller for identifying a unit in a solid state memory device for writing data to

InventorID:

1031285 ⎘