Plano, Texas
United States
16
2026-04-02
The entities that hold a legal rights for patent applications filed by inventor Weiser Doug:
Doug Weiser from Plano, US has applied for patents for these inventions. The list has both pending applications and granted patents:
JUNCTION DIODE ISOLATION
#2 | 2025-03-06ASYMMETRICAL CHANNEL FLOATING GATE THREE-STATE ONE-TIME PROGRAMMABLE NONVOLATILE MEMORY
#3 | 2024-12-05BURIED CHANNEL SEMICONDUCTOR DEVICE INCLUDING ENERGY BARRIER MODULATION REGION(S)
#4 | 2020-12-24Method and structure for dual sheet resistance trimmable thin film resistors
#5 | 2020-07-09High voltage demos transistor with improved threshold voltage matching
#6 | 2019-10-10High density wafer level test module
#7 | 2019-07-04High voltage DEMOS transistor with improved threshold voltage matching
#8 | 2019-01-17Integrated JFET structure with implanted backgate
#9 | 2019-01-03Programmable non-volatile memory with low off current
#10 | 2018-09-13Method and structure for dual sheet resistance trimmable thin film resistors
#11 | 2018-01-18Method and structure for dual sheet resistance trimmable thin film resistors at same level
#12 | 2017-12-28Integrated JFET structure with implanted backgate
#13 | 2016-11-03Silicon IMPATT diode
#14 | 2015-01-22Integration of the silicon IMPATT diode in an analog technology
#15 | 2011-03-03Semiconductor wafer having test modules including pin matrix selectable test devices
#16 | 2005-06-09Modeling process for integrated circuit film resistors
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