Prashant U. Kenkare

Method and apparatus for read assist to achieve robust static random access memory (SRAM)

Integrated clock gater (ICG) using clock cascode complimentary switch logic

Integrated clock gater (ICG) using clock cascode complimentary switch logic

Flip-flop having shared feedback and method of operation

Integrated clock gater (ICG) using clock cascode complimentary switch logic

Memory management unit tag memory

Sequential digital circuitry with test scan

Flip-flop having shared feedback and method of operation

Flip-flop having shared feedback and method of operation

Memory using multiple supply voltages

SRAM with read and write assist

Memory with read cycle write back

Data latch with structural hold

Integrated circuit having memory repair information storage and method therefor

Integrated circuit memory having assisted access and method therefor

Voltage-based memory size scaling in a data processing system

Memory having negative voltage write assist circuit and method therefor

Integrated circuit having boosted array voltage and method therefor

Single-supply, single-ended level conversion circuit for an integrated circuit having multiple power supply domains

One time programmable element system in an integrated circuit

Bitcell with variable-conductance transfer gate and method thereof

Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access

Multiple port memory with prioritized world line driver and method thereof

System having a memory voltage controller which varies an operating voltage of a memory and method therefor

Memory device having concurrent write and read cycles and method thereof

Memory with increased write margin bitcells

SYSTEM HAVING A CARRY LOOK-AHEAD (CLA) ADDER

Variable switching point circuit

Storage circuit and method therefor

Integrated circuit having a memory with low voltage read/write operation

Data latch with minimal setup time and launch delay

Integrated circuit having a memory with low voltage read/write operation

Programmable cell

Contention-free keeper circuit and a method for contention elimination

Circuit and method for latch bypass

System and method for memory array access with fast address decoder

Storage element with clear operation and method thereof

Storage circuit and method therefor

Dual-port static random access memory having improved cell stability and write margin

Method and apparatus for low voltage write in a static random access memory

SRAM having improved cell stability and method therefor

Memory device with a data hold latch